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A continuous-time delta-sigma ADC with integrated digital background calibration

Tan, Siyu LU ; Miao, Yun; Palm, Mattias; Rodrigues, Joachim Neves LU and Andreani, Pietro LU (2016) In Analog Integrated Circuits and Signal Processing 89(2). p.273-282
Abstract

This work presents a digital calibration technique in continuous-time (CT) delta-sigma (Δ Σ) analog to digital converter. The converter is clocked at 144 MHz with a low oversampling ratio (OSR) of only 8. Dynamic element matching is not efficient to linearize the digital to analog converter (DAC) when the OSR is very low. Therefore, non-idealities in the outermost multi-bit feedback DAC are measured and then removed in the background by a digital circuit. A third-order, four-bit feedback, single-loop CT Δ Σ converter with digital background calibration circuit has been designed, simulated and implemented in 65 nm CMOS process. The maximum simulated signal-to-noise and distortion ratio is 67.1 dB within 9 MHz bandwidth.

Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
Background calibration, Continuous-time, Delta-sigma modulator, Digital calibration
in
Analog Integrated Circuits and Signal Processing
volume
89
issue
2
pages
10 pages
publisher
Springer
external identifiers
  • Scopus:84979987147
ISSN
0925-1030
DOI
10.1007/s10470-016-0800-7
language
English
LU publication?
yes
id
e3c2d070-5be1-43a8-83f9-784138758e0b
date added to LUP
2016-10-13 09:19:09
date last changed
2016-10-13 09:19:09
@misc{e3c2d070-5be1-43a8-83f9-784138758e0b,
  abstract     = {<p>This work presents a digital calibration technique in continuous-time (CT) delta-sigma (Δ Σ) analog to digital converter. The converter is clocked at 144 MHz with a low oversampling ratio (OSR) of only 8. Dynamic element matching is not efficient to linearize the digital to analog converter (DAC) when the OSR is very low. Therefore, non-idealities in the outermost multi-bit feedback DAC are measured and then removed in the background by a digital circuit. A third-order, four-bit feedback, single-loop CT Δ Σ converter with digital background calibration circuit has been designed, simulated and implemented in 65 nm CMOS process. The maximum simulated signal-to-noise and distortion ratio is 67.1 dB within 9 MHz bandwidth.</p>},
  author       = {Tan, Siyu and Miao, Yun and Palm, Mattias and Rodrigues, Joachim Neves and Andreani, Pietro},
  issn         = {0925-1030},
  keyword      = {Background calibration,Continuous-time,Delta-sigma modulator,Digital calibration},
  language     = {eng},
  month        = {11},
  number       = {2},
  pages        = {273--282},
  publisher    = {ARRAY(0x86ea248)},
  series       = {Analog Integrated Circuits and Signal Processing},
  title        = {A continuous-time delta-sigma ADC with integrated digital background calibration},
  url          = {http://dx.doi.org/10.1007/s10470-016-0800-7},
  volume       = {89},
  year         = {2016},
}