Erik Larsson
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- 2012
-
Mark
Re-using Chip Level DFT at Board Level
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Access Time Analysis for IEEE P1687
(
- Contribution to journal › Article
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Mark
Fault management in an IEEE P1687 (IJTAG) environment
2012) 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems p.7-7(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
An MPSoCs demonstrator for fault injection and fault handling in an IEEE P1687 environment
2012) IEEE European Test Symposium (ETS), 2012(
- Contribution to conference › Paper, not in proceeding
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Mark
Test Planning for Core-based 3D Stacked ICs under Power Constraints
2012) IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2012)(
- Contribution to conference › Paper, not in proceeding
-
Mark
The MCNP Monte Carlo Program
2012) p.153-172(
- Chapter in Book/Report/Conference proceeding › Book chapter
- 2011
-
Mark
Adaptive Execution Assistance for Multiplexed Fault-Tolerant Chip Multiprocessors
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
European Test Symposium (ETS) 2011
(
- Contribution to specialist publication or newspaper › Specialist publication article