Ping Lu (Former)
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- 2012
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Mark
A 3.6mW, 90nm CMOS Gated-Vernier Time-to-Digital Converter with an Equivalent Resolution of 3.2ps
(
- Contribution to journal › Article
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Mark
A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS
2012) GigaHertz Symposium 2012(
- Contribution to conference › Abstract
- 2011
-
Mark
A 5GHz 90-nm CMOS all digital phase-locked loop
(
- Contribution to journal › Article
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Mark
A mixed mode design flow for multi GHz ADPLLs
2011) 29th Norchip conference, 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 90nm CMOS Gated-Ring-Oscillator-Based Vernier Time-to-Digital Converter with Improved Resolution
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A Digital PLL with a Multi-Delay Coarse-Fine TDC
2011) 29th Norchip conference, 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 0.13µm CMOS ΔΣ PLL FM Transmitter
2011) 29th Norchip conference, 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS
2011) 29th Norchip conference, 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2010
-
Mark
A High-resolution Vernier Gated-Ring-Oscillator TDC in 90-nm CMOS
2010) NORCHIP Conference, 2010(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2009
-
Mark
A 5.4GHz wide tuning range CMOS PLL using an auto-calibration multiple-pass ring oscillator
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding