Ping Lu (Former)
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- 2009
-
Mark
A 5GHz 90-nm CMOS all digital phase-locked loop
(
- Contribution to conference › Paper, not in proceeding
- 2008
-
Mark
A 5.4GHz 90-nm CMOS digitally controlled LC oscillator with 21% tuning range, 1.1MHz resolution, and 180dB FOM
2008) Norchip Conference, 2008(
- Contribution to conference › Paper, not in proceeding
- 2007
-
Mark
A low-jitter clock generator for HDTV
(
- Contribution to journal › Article
-
Mark
A 4 GHz ring oscillator based on dual-feedback loops with PVT deviation adaption
(
- Contribution to journal › Article
- 2006
-
Mark
A 4.6GHz PLL with automatic frequency calibration based on multiple-pass ring oscillator
2006) The IET International Conference on Wireless, Mobile and Multimedia Networks(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A low-jitter frequency synthesizer with dynamic phase interpolation for high-speed Ethernet
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 12-bit 125-MHz segmented current-steering DAC for communication application
2006) The IET International Conference on Wireless, Mobile and Multimedia Networks(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A low-jitter and low-power frequency synthesizer applied to 1000 Base-T Ethernet
(
- Contribution to journal › Article
- 2005
-
Mark
Delay-locked loop and its applications
(
- Contribution to journal › Article
-
Mark
A 3.3v low-jitter frequency Synthesizer applied to fast Ethernet transceiver
(
- Contribution to journal › Article