@inproceedings{3442ea4d-270f-4e1e-ac4e-46dea5478659,
  abstract     = {{<p>The Posit number system features tapered precision, providing higher accuracy for values near unity while maintaining a wide dynamic range, making the format an attractive alternative to IEEE 754 for machine-learning workloads. This work presents CPAU, a unified and configurable Posit arithmetic architecture that integrates a quire-based MAC unit and a general-purpose execution unit supporting addition, multiplication, division, exponential, and square root. CPAU employs a shared decode-execute-encode pipeline across all operators, substantially reducing hardware cost while preserving accuracy in serial computations. A dedicated exponential unit enables full softmax evaluation directly in the Posit domain without format conversions. Synthesis in a 22 nm technology demonstrates significant area improvements of more than 34% and 50% for multiplier and adder area, respectively. Moreover, the implementation of exponential function provides the functionality required for inference and training.</p>}},
  author       = {{Wu, Yue and Mammadzada, Fuad and Westring, Kristoffer and Rodrigues, Joachim}},
  booktitle    = {{24th IEEE Interregional NEWCAS Conference, NEWCAS 2026 : an IEEE CASS flagship conference. June 21-24, 2026, Saguenay, Québec, Canada:  proceedings}},
  isbn         = {{979-8-3315-4413-3}},
  keywords     = {{Decode; Encode; Exponential; ML training; Posit arithmetic; Softmax}},
  language     = {{eng}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  series       = {{24th IEEE Interregional NEWCAS Conference, NEWCAS 2026 - Proceedings}},
  title        = {{CPAU : a hardware efficient configurable posit arithmetic unit}},
  url          = {{http://dx.doi.org/10.1109/NewCAS64543.2026.11674051}},
  doi          = {{10.1109/NewCAS64543.2026.11674051}},
  year         = {{2026}},
}