@inproceedings{3fe3b1a0-ae2b-4c19-ae1e-8e941464ae1b,
  abstract     = {{Semiconductors use built-in logic to perform test, validation, and other operational activities over the lifetime of the device. These test features, referred to as instruments, become a security risk, as they provide high observability and controllability of the device. The fear is that an adversary could exploit these instruments with malicious intent. <br/><br/>We have analyzed and developed security measures against multiple threats over the semiconductor life-cycle, during our work on the Chips JU project: Resilient Trust. In this paper, the security measures we have proposed are applied to a demonstrator circuit implemented on FPGA. The demonstrator is composed of a small IEEE Std. 1687 (IJTAG) network, which provides access to on-chip test instruments. This paper illustrates how the proposed security measures are implemented and working in conjunction to protect a system against attacks. Finally, several attacks are applied to the demonstrator circuit, to show the security measures in action.}},
  author       = {{Åhlund, Joel and Törmänen, Markus and Larsson, Erik}},
  booktitle    = {{2026 IEEE International Conference on Cyber Security and Resilience (CSR) : CSR Workshop on Resilient Trust (R-T)}},
  language     = {{eng}},
  month        = {{08}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{Protecting on-chip test instrumentation : resilient trust demonstrator}},
  year         = {{2026}},
}