@inproceedings{7fddeb7e-e4e1-42c8-9556-778bdeecda76,
  abstract     = {{Approximate multipliers (AMs) show great potential to achieve substantial area and power savings when replacing their exact counterparts in error-resilient applications. In this paper, we propose an AM architecture, scalable across operand widths. Our 8-bit AM achieves a 1.91% Mean Relative Error Distance (MRED) and a power-area-delay product (PADP) gain of >78.2% over a Wallace multiplier. We also introduce an evaluation methodology focused on post-implementation hardware savings. Beyond standalone benchmarking, measurements of a 22nm chip confirm substantial power reductions of 32.9% when replacing exact multipliers with our AM.}},
  author       = {{Åberg, Victor and Castillo Mohedano, Sergio and Westring, Kristoffer and Allfjord, Alex and Andersson, Per and Rodrigues, Joachim and Nouripayam, Masoud}},
  booktitle    = {{2026 IEEE European Solid-State Electronics Research Conference (ESSERC)}},
  language     = {{eng}},
  title        = {{Scalable and power efficient approximate multipliers for error-resilient applications in 22 nm}},
  year         = {{2026}},
}