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- 2005
-
Mark
Accurate sample-and-hold circuit model
(
- Contribution to journal › Article
-
Mark
Silent CMOS circuits aiming for system-on-chip
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Design considerations of a floating-point ADC with embedded S/H
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A Reconfigurable Pipelined ADC in 0.18 um CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Studies of time error limitations in ADC systems with random parallel passive sampling
2005) Swedish System-on-Chip Conference (SSoCC'05)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2004
-
Mark
A single-stage direct interpolation multiphase clock generator with phase error averaging
(
- Contribution to journal › Article
-
Mark
An accurate circuit model for a general sample-and-hold circuit
2004) 2004 IEEJ (7th) International Analog VLSI Workshop (AVLSIWS 2004)(
- Contribution to conference › Paper, not in proceeding
-
Mark
A simulation model for embedding the transistor bias
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A novel reconfigurable pipelined A/D conversion technique for multistandard wideband receivers
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A CMOS 500 MS/S charge sampler
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding