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- 2018
-
Mark
A Self-aligned Gate-last Process applied to All-III-V CMOS on Si
(
- Contribution to journal › Article
- 2017
-
Mark
Vertical III-V Nanowire Tunnel Field-Effect Transistor
2017)(
- Thesis › Doctoral thesis (compilation)
- 2016
-
Mark
Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si
(
- Contribution to journal › Letter
- 2015
-
Mark
Vertical InAs Nanowire Devices and RF Circuits
(
- Thesis › Doctoral thesis (compilation)
- 2007
-
Mark
Statistical rate allocation for layered space-time structure
(
- Contribution to journal › Article