1 – 10 of 13
- show: 10
- |
- sort: year (new to old)
Close
Embed this list
<iframe src=" "
width=" "
height=" "
allowtransparency="true"
frameborder="0">
</iframe>
- 2019
-
Mark
A high precision logarithmic-curvature compensated all CMOS voltage reference
(
- Contribution to journal › Article
-
Mark
A 10-mW mm-Wave Phase-Locked Loop With Improved Lock Time in 28-nm FD-SOI CMOS
(
- Contribution to journal › Article
- 2015
-
Mark
A 128-channel discrete cosine transform-based neural signal processor for implantable neural recording microsystems
(
- Contribution to journal › Article
- 2011
-
Mark
Time-variant analysis and design of a power efficient ISM-band quadrature receiver
(
- Contribution to journal › Article
-
Mark
Design and analysis of an ultra-low-power LC quadrature VCO
(
- Contribution to journal › Article
-
Mark
Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2003
-
Mark
Custom Datapaths for DSP ASICs Methodology and Implementation
2003)(
- Thesis › Doctoral thesis (compilation)
- 1999
-
Mark
Power Reduction in Custom CMOS Digital Filter Structures
(
- Contribution to journal › Article