A low-complexity VLSI architecture for square root MIMO detection
(2003) IASTED International Conference on Circuits, Signals and Systems, 2003 p.304-309- Abstract
- Low-complexity VLSI (very large scale integration) architecture of the square root algorithm is proposed for MIMO (multiple-input multiple-output) detection. As a modification to the traditional QR triangular array based architecture, the proposed architecture significantly reduces the area and power consumption with virtually no performance or throughput degradation. The finite word length effects specific to the architecture are analyzed considering trade-offs between the performance and the hardware cost. The proposed VLSI architecture is implemented on a VirtexE series Xilinx FPGA (field programmable gate arrays). For a 4-transmit and 4-receive antennas MIMO system using QPSK (quarter phase-shift keying) modulation scheme, a detecting... (More)
- Low-complexity VLSI (very large scale integration) architecture of the square root algorithm is proposed for MIMO (multiple-input multiple-output) detection. As a modification to the traditional QR triangular array based architecture, the proposed architecture significantly reduces the area and power consumption with virtually no performance or throughput degradation. The finite word length effects specific to the architecture are analyzed considering trade-offs between the performance and the hardware cost. The proposed VLSI architecture is implemented on a VirtexE series Xilinx FPGA (field programmable gate arrays). For a 4-transmit and 4-receive antennas MIMO system using QPSK (quarter phase-shift keying) modulation scheme, a detecting throughput of 80 Mb/s can be achieved (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/612575
- author
- Guo, Zhan LU and Nilsson, Peter LU
- organization
- publishing date
- 2003
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- multiple-input multiple-output, square root algorithm, power consumption, finite word length analysis, VirtexE series Xilinx FPGA, field programmable gate arrays, 4-transmit antennas, quarter phase-shift keying, 4-receive antennas, QPSK modulation, MIMO detection, VLSI architecture, very large scale integration
- host publication
- Proceedings of the IASTED International Conference on Circuits, Signals, and Systems
- pages
- 304 - 309
- publisher
- ACTA Press
- conference name
- IASTED International Conference on Circuits, Signals and Systems, 2003
- conference location
- Cancun, Mexico
- conference dates
- 2003-05-19 - 2003-05-21
- external identifiers
-
- scopus:1542316944
- ISBN
- 0-88986-351-2
- language
- English
- LU publication?
- yes
- id
- 905439c5-52f1-41bd-bb21-f6a7677d2ab3 (old id 612575)
- date added to LUP
- 2016-04-04 12:18:21
- date last changed
- 2022-04-24 02:00:59
@inproceedings{905439c5-52f1-41bd-bb21-f6a7677d2ab3, abstract = {{Low-complexity VLSI (very large scale integration) architecture of the square root algorithm is proposed for MIMO (multiple-input multiple-output) detection. As a modification to the traditional QR triangular array based architecture, the proposed architecture significantly reduces the area and power consumption with virtually no performance or throughput degradation. The finite word length effects specific to the architecture are analyzed considering trade-offs between the performance and the hardware cost. The proposed VLSI architecture is implemented on a VirtexE series Xilinx FPGA (field programmable gate arrays). For a 4-transmit and 4-receive antennas MIMO system using QPSK (quarter phase-shift keying) modulation scheme, a detecting throughput of 80 Mb/s can be achieved}}, author = {{Guo, Zhan and Nilsson, Peter}}, booktitle = {{Proceedings of the IASTED International Conference on Circuits, Signals, and Systems}}, isbn = {{0-88986-351-2}}, keywords = {{multiple-input multiple-output; square root algorithm; power consumption; finite word length analysis; VirtexE series Xilinx FPGA; field programmable gate arrays; 4-transmit antennas; quarter phase-shift keying; 4-receive antennas; QPSK modulation; MIMO detection; VLSI architecture; very large scale integration}}, language = {{eng}}, pages = {{304--309}}, publisher = {{ACTA Press}}, title = {{A low-complexity VLSI architecture for square root MIMO detection}}, year = {{2003}}, }