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- 2024
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Mark
Source Design of Vertical III-V Nanowire Tunnel Field-Effect Transistors
(
- Contribution to journal › Article
- 2023
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Mark
Sensing single domains and individual defects in scaled ferroelectrics
(
- Contribution to journal › Article
-
Mark
Geometric control of diffusing elements on InAs semiconductor surfaces via metal contacts
(
- Contribution to journal › Article
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Mark
High-k/InGaAs interface defects at cryogenic temperature
(
- Contribution to journal › Article
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Mark
Dynamics of Polarization Switching in Mixed Phase Ferroelectric-Antiferroelectric HZO Thin Films
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
gm/Id Analysis of vertical nanowire III–V TFETs
(
- Contribution to journal › Letter
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Mark
Reconfigurable signal modulation in a ferroelectric tunnel field-effect transistor
(
- Contribution to journal › Article
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Mark
High Current Density Vertical Nanowire TFETs With I₆₀ > 1
μ
A/
μ
m
(
- Contribution to journal › Article
-
Mark
Self-Heating in Gate-All-Around Vertical III-V InAs/InGaAs MOSFETs
(
- Contribution to journal › Article
-
Mark
Effects of Interface Oxidation on Noise Properties and Performance in III–V Vertical Nanowire Memristors
(
- Contribution to journal › Article
-
Mark
Low-Power, Self-Aligned Vertical InGaAsSb NW PMOS With S < 100 mV/dec
(
- Contribution to journal › Article
- 2022
-
Mark
The Effect of Deposition Conditions on Heterointerface-Driven Band Alignment and Resistive Switching Properties
(
- Contribution to journal › Article
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Mark
A 4F2 Vertical Gate-all-around Nanowire Compute-in-memory Device Integrated in (1T1R) Cross-Point Arrays on Silicon
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Low-Frequency Noise in Vertical InAs/InGaAs Gate-All-Around MOSFETs at 15 K for Cryogenic Applications
(
- Contribution to journal › Article
-
Mark
Lateral III-V Nanowire MOSFETs in Low-Noise Amplifier Stages
(
- Contribution to journal › Article
-
Mark
As-deposited ferroelectric HZO on a III–V semiconductor
(
- Contribution to journal › Article
-
Mark
Directed Self‐Assembly for Dense Vertical III–V Nanowires on Si and Implications for Gate All‐Around Deposition
(
- Contribution to journal › Article
-
Mark
Improved Electrostatics through Digital Etch Schemes in Vertical GaSb Nanowire p-MOSFETs on Si
(
- Contribution to journal › Article
-
Mark
Performance, Analysis, and Modeling of III-V Vertical Nanowire MOSFETs on Si at Higher Voltages
(
- Contribution to journal › Article
-
Mark
Integration of Ferroelectric HfxZr1-xO2 on Vertical III-V Nanowire Gate-All-Around FETs on Silicon
(
- Contribution to journal › Article