@misc{9225905,
  abstract     = {{In the hardware development space, field programmable gate arrays (FPGAs) are
in a unique position as a result of their in-field re-programmability. In contrast
to the traditional design process of integrated circuits, FPGAs allow iterative de-
velopment workflows closely resembling software development’s sprint-based pro-
totyping. For this to work, efficient workflows for verification are key. Verification
can be done through simulators, but for complex designs with intricate depen-
dencies of surrounding hardware, these are not always sufficient. For such cases,
in-circuit debugging solutions can be utilized. These represent debugging cores
that are implemented on the FPGA silicon itself, capable of monitoring internal
signals during system runtime.
In this master’s thesis project, a debugging system has been developed. It
was designed to provide a convenient and resource efficient way to perform post-
implementation in-circuit verification of FPGA designs. The debugging system
was made to be configurable and controlled through a Python library, allowing
extensive scripting and unit-testing capabilities. The debugging system is ven-
dor and platform agnostic and easy to integrate into a pre-existing Python-based
verification workflow. We evaluated our system by comparing metrics such as ease-
of-use, functionality, and resource consumption against Xilinx Vivado’s Integrated
Logic Analyzer (ILA).}},
  author       = {{Sjödin, Hugo and Stenroos, Jonathan}},
  language     = {{eng}},
  note         = {{Student Paper}},
  title        = {{Python-based Trace and Debug of FPGA Designs}},
  year         = {{2026}},
}