@misc{9234901,
  abstract     = {{With growing complexity of developing Application-Specific Integrated Circuit
(ASIC), comes a higher development time, in both designing and verifying Reg-
ister Transfer Level (RTL) code. Configurability can reduce the time spent on
re-designing, and instead replace with simple reconfiguration. The configurable
design then typically need initial verification effort.
This thesis seeks to investigate the possibilities of making the Clock and Reset
Controller (CCR) block more configurable, both in terms of run-time and compile-
time configurability. The configurability makes the interface and logic of modules
more predictable which more easily enable reusability in the verification frame-
work. However, as concluded in the thesis, using SystemVerilog language features
for configurability can reduce the readability of the RTL code. Code generation
can be used to generate more readable RTL files, but can be harder to implement.
The thesis investigates different run-time Finite State Machine (FSM) architec-
tures suitable for CCR, and choses one for implementation. The results show that
the design sets constraints on the functionalities of the FSM and can come with
increased area and power, but can save from expensive re-tapeouts in case of faulty
implemented logic.
Clock division and clock muxing are critical features used throughout the CCR.
The thesis investigates current clock division and clock muxing designs and pro-
poses new implementations, that can be configured for in the CCR. The proposed
clock mux implementation has less area, power, critical path and faster transi-
tion time, than using traditional 2 input glitch free multiplexers, according to our
measurements. However, more testing would need to be done.
One technique to integrate third-party Intellectual Propertys (IPs) is to design
a wrapper module. A unified Phase-Locked Loop (PLL) wrapper interface was
designed, that can integrate a variety of PLLs. The thesis also proposes a gen-
eral software automation flow, where code generation is used to integrate a PLL
wrapper, through defining pin connections and configurations in a spreadsheet.}},
  author       = {{Tegnvallius Boklund, Alexander and Strömberg, Ture}},
  language     = {{eng}},
  note         = {{Student Paper}},
  title        = {{Configurable Central Clock and Reset Controller}},
  year         = {{2026}},
}