@misc{9235207,
  abstract     = {{As transistors get smaller and smaller, the power density of an integrated circuit increases and thus the temperature increases. In an application specific integrated circuit (ASIC) the layout is tailor-made for each design, so the thermal signature of each component can be taken into account during the floorplanning process. Although approaches for thermal aware floorplanning exists, they aren't generalizable to new floorplans and can't handle hierarchical structures adequately. In this thesis we present a method to do thermal-aware compact floorplanning that is also generalizable through the use of reinforcement learning. We present a novel way to do hierachical divisions within the ASIC to improve connectivity, a new fast analytical thermal simulator and also utilize simulated annealing with reinforcement learning (SARL) in VLSI floorplanning for the first time. Our results are very successful demonstrating an automated flow for generating thermal aware floorplans.}},
  author       = {{Biswas, Soumya and Franzén, Albin}},
  language     = {{eng}},
  note         = {{Student Paper}},
  title        = {{Thermal Aware Floorplan Techniques for ASICs}},
  year         = {{2026}},
}