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- 2021
-
Mark
Customization of Ibex RISC-V Processor Core
2021) In Customization of Ibex RISC-V Processor Core EITM02 20211(
Department of Electrical and Information Technology- Master (Two yrs)
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Mark
Design parameterizable filter using High Level Synthesis
(
- Master (Two yrs)
- 2020
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Mark
Implementation of a Deep Learning Inference Accelerator on the FPGA.
(
- Master (Two yrs)
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Mark
Low Power Pre-Distorter Design For 5G Radio Using Machine Learning
(
- Master (Two yrs)
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Mark
Self-organizing Maps for Digital Pre-distortion
(
- Master (Two yrs)
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Mark
High-Level Synthesis for Efficient Design and Verification
(
- Master (Two yrs)
- 2019
-
Mark
Implementation of an 8-bit Dynamic Fixed-Point Convolutional Neural Network for Human Sign Language Recognition on a Xilinx FPGA Board
(
- Master (Two yrs)
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Mark
Investigate Redundancy In Sounding Reference Signal Based Channel Estimates
(
- Master (Two yrs)
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Mark
Reduction of Crosstalk Distortion in 5G
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- Master (Two yrs)
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Mark
Arbitrary Decimation for High Sample Rates, Algorithm Design and FPGA implementation
(
- Master (Two yrs)