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- 2020
-
Mark
Digital Design Flow Techniques and Circuit Design for Thin-Film Transistors
(
- Master (Two yrs)
-
Mark
Gate Recurrent Unit Neural Networks for Hearing Instruments
(
- Master (Two yrs)
-
Mark
A Hardware Accelerated Low Power DSP for Recurrent Neural Networks
(
- Master (Two yrs)
-
Mark
FPGA Implementation of an Anonymization Algorithm
(
- Master (Two yrs)
- 2019
-
Mark
DSP Design With Hardware Accelerator For Convolutional Neural Networks
(
- Master (Two yrs)
-
Mark
Spice Circuit Reduction for Speeding up Simulation and Verification
(
- Master (Two yrs)
- 2017
-
Mark
Integration of a Digital Built-in Self-Test for On-Chip Memories
(
- Master (Two yrs)
- 2016
-
Mark
Design of a Memory Compiler
(
- Master (Two yrs)
-
Mark
Turbo Decoder with early stopping criteria
(
- Master (Two yrs)
- 2015
-
Mark
High Level Synthesis for Design of Video Processing Blocks
(
- Master (Two yrs)