Enhancing Analysis of Hardware Design Verification Metrics Using Machine Learning & Data Visualization
(2021) EITM01 20202Department of Electrical and Information Technology
- Abstract
- Closing coverage holes during verification of digital integrated circuits is an iterative process to guarantee all parts are verified before fabrication. The time and manpower it takes to close coverage holes extend with the increasing complexity and size of a digital circuit.
In this thesis unsupervised machine learning is used to cluster together related coverage holes, providing aid for a verification engineer to see a connection between uncovered coverage holes present in a digital RTL design. The coverage metrics are first extracted from a coverage database along with information of the RTL, the data is then pre-processed to prepare it for clustering. The coverage holes are clustered together with the OPTICS, affinity propagation... (More) - Closing coverage holes during verification of digital integrated circuits is an iterative process to guarantee all parts are verified before fabrication. The time and manpower it takes to close coverage holes extend with the increasing complexity and size of a digital circuit.
In this thesis unsupervised machine learning is used to cluster together related coverage holes, providing aid for a verification engineer to see a connection between uncovered coverage holes present in a digital RTL design. The coverage metrics are first extracted from a coverage database along with information of the RTL, the data is then pre-processed to prepare it for clustering. The coverage holes are clustered together with the OPTICS, affinity propagation and $k$-means algorithms.
Observation shows that clustering together the coverage holes can reveal which holes are related to each other and that a potential solution for one of them have a high chance at also fixing the related holes.
This can be used by verification engineers to optimize the task of closing coverage holes. The resources spent on verification can then be reduced to save cost on development. (Less)
Please use this url to cite or link to this publication:
http://lup.lub.lu.se/student-papers/record/9047586
- author
- Uggla, Oscar LU and Voss, Axel
- supervisor
-
- Erik Larsson LU
- organization
- course
- EITM01 20202
- year
- 2021
- type
- H2 - Master's Degree (Two Years)
- subject
- report number
- LU/LTH-EIT 2021-812
- language
- English
- id
- 9047586
- date added to LUP
- 2021-06-02 11:08:38
- date last changed
- 2021-06-02 11:08:38
@misc{9047586,
abstract = {{Closing coverage holes during verification of digital integrated circuits is an iterative process to guarantee all parts are verified before fabrication. The time and manpower it takes to close coverage holes extend with the increasing complexity and size of a digital circuit.
In this thesis unsupervised machine learning is used to cluster together related coverage holes, providing aid for a verification engineer to see a connection between uncovered coverage holes present in a digital RTL design. The coverage metrics are first extracted from a coverage database along with information of the RTL, the data is then pre-processed to prepare it for clustering. The coverage holes are clustered together with the OPTICS, affinity propagation and $k$-means algorithms.
Observation shows that clustering together the coverage holes can reveal which holes are related to each other and that a potential solution for one of them have a high chance at also fixing the related holes.
This can be used by verification engineers to optimize the task of closing coverage holes. The resources spent on verification can then be reduced to save cost on development.}},
author = {{Uggla, Oscar and Voss, Axel}},
language = {{eng}},
note = {{Student Paper}},
title = {{Enhancing Analysis of Hardware Design Verification Metrics Using Machine Learning & Data Visualization}},
year = {{2021}},
}