High Level Synthesis for Design of Video Processing Blocks
(2015) EITM01 20142Department of Electrical and Information Technology
- Abstract (Swedish)
- Nowadays the technology is progressing continuously. The designers are developing products with new features and always giving to the user an innovative technological solution for the society problems. The standard methods to design new devices are becoming slower for the demand of the products. Due to this growing complexity, some possible substitutes of the traditional Register Transfer Level (RTL) design flow has been appeared. This situation is becoming a bigger problem which needs to be solved and that is why many opened researches exist about it.
In the early 90s started the idea of High Level Synthesis (HLS) and in the actual market is getting more relevance like a substitution of the standard designing methods. In a brief... (More) - Nowadays the technology is progressing continuously. The designers are developing products with new features and always giving to the user an innovative technological solution for the society problems. The standard methods to design new devices are becoming slower for the demand of the products. Due to this growing complexity, some possible substitutes of the traditional Register Transfer Level (RTL) design flow has been appeared. This situation is becoming a bigger problem which needs to be solved and that is why many opened researches exist about it.
In the early 90s started the idea of High Level Synthesis (HLS) and in the actual market is getting more relevance like a substitution of the standard designing methods. In a brief description, High Level Synthesis is an automatic compilation technique that translates a software program to a hardware circuit. The critical step to jump to this new field is if High Level Synthesis will give to the designers, at least, the same design possibilities and the same quality of results as handwritten hardware design. During the last ten years many companies and academic organizations has emerged which have been developing new tools for High Level Synthesis.
The scope of this Master's Thesis is to evaluate one of these commercial tools (Catapult from Calypto), to understand the possibilities and the limitations of it. The purpose of the thesis is to study, analyze and test the tool with reference models (video blocks) provided by ARM Sweden. The handwritten RTL description of the models, were provided by ARM to be used to verify and compare the correctness and the QoR (Quality of Results) of the RTL generated by the HLS tool, Catapult.
After developing the Master's Thesis, Catapult obtained the same functionality, the same performance and the same operating frequency with all the blocks worked with. However, the principal limitation of Catapult that was experienced during the work, is the total area of the generated RTL in more complex designs. The two larger designs developed in Catapult resulted in a larger area score result after synthesis compared with the handwritten RTL. Apart from this issue, HLS gives a huge advantage in comparison with handwritten RTL: the short time it takes to develop a complete hardware design and the possibility to explore different area/performance trade-off. (Less)
Please use this url to cite or link to this publication:
http://lup.lub.lu.se/student-papers/record/5212063
- author
- Chabouk Jokhadar, Ayla LU and Gomez Gonzalez, Carlos LU
- supervisor
- organization
- course
- EITM01 20142
- year
- 2015
- type
- H2 - Master's Degree (Two Years)
- subject
- keywords
- HLS High Level Synthesis Catapult
- language
- English
- id
- 5212063
- date added to LUP
- 2015-03-26 16:36:56
- date last changed
- 2015-03-26 16:36:56
@misc{5212063,
abstract = {{Nowadays the technology is progressing continuously. The designers are developing products with new features and always giving to the user an innovative technological solution for the society problems. The standard methods to design new devices are becoming slower for the demand of the products. Due to this growing complexity, some possible substitutes of the traditional Register Transfer Level (RTL) design flow has been appeared. This situation is becoming a bigger problem which needs to be solved and that is why many opened researches exist about it.
In the early 90s started the idea of High Level Synthesis (HLS) and in the actual market is getting more relevance like a substitution of the standard designing methods. In a brief description, High Level Synthesis is an automatic compilation technique that translates a software program to a hardware circuit. The critical step to jump to this new field is if High Level Synthesis will give to the designers, at least, the same design possibilities and the same quality of results as handwritten hardware design. During the last ten years many companies and academic organizations has emerged which have been developing new tools for High Level Synthesis.
The scope of this Master's Thesis is to evaluate one of these commercial tools (Catapult from Calypto), to understand the possibilities and the limitations of it. The purpose of the thesis is to study, analyze and test the tool with reference models (video blocks) provided by ARM Sweden. The handwritten RTL description of the models, were provided by ARM to be used to verify and compare the correctness and the QoR (Quality of Results) of the RTL generated by the HLS tool, Catapult.
After developing the Master's Thesis, Catapult obtained the same functionality, the same performance and the same operating frequency with all the blocks worked with. However, the principal limitation of Catapult that was experienced during the work, is the total area of the generated RTL in more complex designs. The two larger designs developed in Catapult resulted in a larger area score result after synthesis compared with the handwritten RTL. Apart from this issue, HLS gives a huge advantage in comparison with handwritten RTL: the short time it takes to develop a complete hardware design and the possibility to explore different area/performance trade-off.}},
author = {{Chabouk Jokhadar, Ayla and Gomez Gonzalez, Carlos}},
language = {{eng}},
note = {{Student Paper}},
title = {{High Level Synthesis for Design of Video Processing Blocks}},
year = {{2015}},
}