Complexity Reduction in the CORDIC Algorithm by using MUXes
(2015) EITM02 20142Department of Electrical and Information Technology
- Abstract
- Nowadays, the CORDIC algorithm plays an important role to deal with the non-linear functions in hardware. In this thesis, a novel methodology is described to reduce the complexity in an unrolled CORDIC architecture, which gives higher speed, lesser area, and lower power consumption. That is, MUXes are used to replace adder stages. Five different unrolled CORDIC architectures have been implemented in ASIC using a 65nm CMOS technology with Low Power High V_T transistors. The area, computational speed, accuracy, error behavior, and power consumption have been analyzed. The design aim is to reduce the power consumption, which is more and more important depending on the area. As a result the area and power consumption get 7.9% lower and 27.2%... (More)
- Nowadays, the CORDIC algorithm plays an important role to deal with the non-linear functions in hardware. In this thesis, a novel methodology is described to reduce the complexity in an unrolled CORDIC architecture, which gives higher speed, lesser area, and lower power consumption. That is, MUXes are used to replace adder stages. Five different unrolled CORDIC architectures have been implemented in ASIC using a 65nm CMOS technology with Low Power High V_T transistors. The area, computational speed, accuracy, error behavior, and power consumption have been analyzed. The design aim is to reduce the power consumption, which is more and more important depending on the area. As a result the area and power consumption get 7.9% lower and 27.2% lower separately, and the speed is 22.9% higher compared to the original unrolled CORDIC architecture. (Less)
Please use this url to cite or link to this publication:
http://lup.lub.lu.se/student-papers/record/7862224
- author
- Sun, Yuhang LU
- supervisor
- organization
- course
- EITM02 20142
- year
- 2015
- type
- H2 - Master's Degree (Two Years)
- subject
- keywords
- CORDIC, power consumption
- report number
- LU/LTH-EIT 2015-460
- language
- English
- id
- 7862224
- date added to LUP
- 2015-09-22 08:21:18
- date last changed
- 2015-09-22 08:21:18
@misc{7862224, abstract = {{Nowadays, the CORDIC algorithm plays an important role to deal with the non-linear functions in hardware. In this thesis, a novel methodology is described to reduce the complexity in an unrolled CORDIC architecture, which gives higher speed, lesser area, and lower power consumption. That is, MUXes are used to replace adder stages. Five different unrolled CORDIC architectures have been implemented in ASIC using a 65nm CMOS technology with Low Power High V_T transistors. The area, computational speed, accuracy, error behavior, and power consumption have been analyzed. The design aim is to reduce the power consumption, which is more and more important depending on the area. As a result the area and power consumption get 7.9% lower and 27.2% lower separately, and the speed is 22.9% higher compared to the original unrolled CORDIC architecture.}}, author = {{Sun, Yuhang}}, language = {{eng}}, note = {{Student Paper}}, title = {{Complexity Reduction in the CORDIC Algorithm by using MUXes}}, year = {{2015}}, }