Hardware Implementation of a 32-point Radix-2 FFT Architecture
(2015) EITM02 20151Department of Electrical and Information Technology
- Abstract
- The Fast Fourier Transform (FFT) algorithm has been widely used in the Digital Signal Processing industry as a rudimentary operation to select the specific frequency components of a signal, which has been involved with other time domain signals. In order to fulfill the requirements of executing precise calculations and less power & area consumption, an algorithm with less number of adders and multipliers is used.
In this thesis, a radix-2 32-point FFT algorithm, which is using Decimation- In-Frequency (DIF) , is implemented in VHDL. In addition, the implementation is designed for a 65nm CMOS process. The ASIC verification process is tested and implemented, by using Synthesis, Post-synthesis Simulation, Place & Route, Post-layout... (More) - The Fast Fourier Transform (FFT) algorithm has been widely used in the Digital Signal Processing industry as a rudimentary operation to select the specific frequency components of a signal, which has been involved with other time domain signals. In order to fulfill the requirements of executing precise calculations and less power & area consumption, an algorithm with less number of adders and multipliers is used.
In this thesis, a radix-2 32-point FFT algorithm, which is using Decimation- In-Frequency (DIF) , is implemented in VHDL. In addition, the implementation is designed for a 65nm CMOS process. The ASIC verification process is tested and implemented, by using Synthesis, Post-synthesis Simulation, Place & Route, Post-layout Simulation, and Prime Time. Results regarding area, throughput, and power consumption are presented. (Less) - Popular Abstract
- This thesis report is about the hardware implementation of 32-point Radix- 2 FFT Architecture.
The modeling part is done in MATLAB. The algorithm for the realization of the FFT in MATLAB modeling part is using the Cooley - Tukey algorithm, which is famous for the radix-2 butterfly. By using the radix-2, the computation complexity is decreasing with fewer numbers of adders and multipliers. Therefore, The area consumption could be saved.
The programming of the design is using VHDL. Since the DIF algorithm is being chosen for this thesis, the input signals are in the positive sequence order and the output signals are half even-indexed, a half odd-indexed time samples. In the hardware programming part, except for the five stages of radix-2... (More) - This thesis report is about the hardware implementation of 32-point Radix- 2 FFT Architecture.
The modeling part is done in MATLAB. The algorithm for the realization of the FFT in MATLAB modeling part is using the Cooley - Tukey algorithm, which is famous for the radix-2 butterfly. By using the radix-2, the computation complexity is decreasing with fewer numbers of adders and multipliers. Therefore, The area consumption could be saved.
The programming of the design is using VHDL. Since the DIF algorithm is being chosen for this thesis, the input signals are in the positive sequence order and the output signals are half even-indexed, a half odd-indexed time samples. In the hardware programming part, except for the five stages of radix-2 butterflies, an additional block is added to the end of the architecture, which is called-”bit reverse”, in order to reverse the order of the output signals into sequence order. Therefore, the results of the 32-point Radix-2 FFT could be used in the next phase. (Less)
Please use this url to cite or link to this publication:
http://lup.lub.lu.se/student-papers/record/7989629
- author
- Gao, Ying ^{LU}
- supervisor
- organization
- course
- EITM02 20151
- year
- 2015
- type
- H2 - Master's Degree (Two Years)
- subject
- keywords
- Radix- 2 FFT, Hardware Implementation, synthesis, place & route, prime time, power consumption
- report number
- LU/LTH-EIT 2015-461
- language
- English
- id
- 7989629
- date added to LUP
- 2015-09-24 10:43:51
- date last changed
- 2015-09-24 10:43:51
@misc{7989629, abstract = {The Fast Fourier Transform (FFT) algorithm has been widely used in the Digital Signal Processing industry as a rudimentary operation to select the specific frequency components of a signal, which has been involved with other time domain signals. In order to fulfill the requirements of executing precise calculations and less power & area consumption, an algorithm with less number of adders and multipliers is used. In this thesis, a radix-2 32-point FFT algorithm, which is using Decimation- In-Frequency (DIF) , is implemented in VHDL. In addition, the implementation is designed for a 65nm CMOS process. The ASIC verification process is tested and implemented, by using Synthesis, Post-synthesis Simulation, Place & Route, Post-layout Simulation, and Prime Time. Results regarding area, throughput, and power consumption are presented.}, author = {Gao, Ying}, keyword = {Radix- 2 FFT,Hardware Implementation,synthesis,place & route,prime time,power consumption}, language = {eng}, note = {Student Paper}, title = {Hardware Implementation of a 32-point Radix-2 FFT Architecture}, year = {2015}, }