Low-Frequency Noise in InGaAs Nanowire MOSFETs

Abstract

Low-frequency (LF) noise (1/f as well as random telegraph-signal (RTS) noise) measurements were performed on high-performance InGaAs nanowire (NW) metal-oxide-semiconductor field-effect transistors (MOSFETs).
1/f noise measurements at room temperature (RT) show that the dominant noise mechanism is carrier number fluctuations. The minimum gate area normalized input gate voltage noise power spectral density (PSD) for these devices is as low as 80 µm^{2}µV^{2}Hz^{-1}, with a corresponding minimum trap density of 9·10 cm^{-3}eV^{-1}, where the calculation of the trap density bases on elastic tunneling of the channel electrons to and from the trap states in the gate oxide. These values are among the lowest for III-V MOSFETs, demonstrating the feasibility of a high-quality, low trap density, high-k gate oxide on InGaAs NW structures. 1/f noise measurements at low temperatures confirm that the dominant noise mechanism is carrier number fluctuations and also give some support for the elastic tunneling model.
RTS noise signals were found in approximately 2/3 of the considered devices, indicating that very few traps influence the electron transport through the channel. It turns out that the capture and emission time constant of a single active trap state change with the applied gate bias. Different models (the elastic tunneling model and the Shockley-Read-Hall (SRH) model) are discussed to explain this behavior. Another striking feature of the RTS noise measurements is the large spread in the RTS noise amplitudes, with maximum amplitudes of up to 1 µA. Simulations of single trap induced subband fluctuations can reproduce this large spread, showing that the magnitude of the RTS noise amplitude is especially sensitive to the position of the trap state along the NW circumference. Temperature-dependent RTS noise measurements reveal a thermal activation of the time constants, which is inconsistent with elastic tunneling but can be explained by multi-phonon-assisted tunneling (inelastic tunneling).

Popular Abstract

Did you know that almost all modern electronic devices (such as smartphones and laptops) consist of a huge number of transistors? In fact, transistors are so essential for these devices that without them they would not work. The increase in performance of smartphones and laptops over the last decades is mainly due to the increase in performance of modern transistors. But what are transistors and how to judge if the transistor performance is good or bad?
Nowadays, the most common realization of a transistor is a metal-oxide-semiconductor field-effect transistor (MOSFET), which consists of three (or four) terminals, namely the source, the drain and the gate. The main idea of a MOSFET is to control the current, flowing from the source to the drain (called the drain current), by a small gate voltage. When the gate voltage is below a certain threshold value, the drain current is (almost) zero and the device is turned off. However, when the gate voltage is bigger than the threshold value, a conducting channel between the source and the drain forms and the drain current starts to flow.
It has been observed decades ago that it would be beneficial for the transistor performance to reduce the device dimensions (the length, the width, and the height), leading, among others, to an increased drain current when the transistor is turned on. Unfortunately, the steady downscaling trend (the newest transistors have a channel length of about 10 nanometers!) leads to a lot of problems. It turns out that some of the problems can be solved by replacing the traditional channel material (Si) by a new material with a higher electron mobility (e.g. InGaAs) and by building the transistors in a nanowire (NW) geometry instead of a planar geometry. A nanowire geometry means that the channel has a cylindrical shape (3D) with the gate all around it.
The downside of using InGaAs as the channel material is that the gate oxide usually forms a bad interface to the channel, resulting in large amount of trap states (crystal defects) in the oxide. These trap states can capture and emit electrons from the channel, giving rise to a randomly fluctuating drain current and degrading the transistor performance. The random fluctuations of the drain current are referred to as electrical noise. If many traps affect the electron transport through the channel (the drain current), the resulting noise will be 1/f noise, meaning that the drain current noise will decrease with increasing noise frequency. If, on the other hand, only one trap affects the electron transport through the channel, the drain current noise will decrease even faster with increasing noise frequency. This type of noise is called random-telegraph-signal (RTS) noise and the characteristic feature of RTS noise is that the drain current switches between two distinctive current levels. One way of judging the transistor performance is based on noise measurements. Roughly speaking, the noisier the transistor, the worse its noise performance.
In my Master thesis, I performed 1/f and RTS noise measurements on InGaAs NW MOSFETs.
1/f noise measurements show very low noise levels, indicating that the electron transport through the channel is limited by very few active traps. On top of that, the low noise levels suggest that it is possible to use a high-quality gate oxide on InGaAs.
To confirm that relatively few traps limit the device performance, I also performed RTS noise measurements. Indeed, there are transistors, in which the current only switches between two levels, showing that only one trap is active.
The 1/f and RTS noise measurements allowed me to extract various properties of the traps, which are useful for engineers to improve future generations of the transistors.

• author: Möhle, Christian Mario
• supervisor: Erik Lind; Claes Thelander
• organization: Solid State Physics; Department of Physics
• course: FYSM60 20171
• year: 2017
• type: H2 - Master's Degree (Two Years)
• subject: Physics and Astronomy
• language: English
• id: 8909007
• date added to LUP: 2017-05-30 09:45:44
• date last changed: 2017-05-30 09:45:44