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Design of Pacman with Debug Logic

Kothamasu, Dinesh LU (2018) EITM02 20181
Department of Electrical and Information Technology
Abstract
This thesis work was performed at Ineda System Pvt Ltd, Hyderabad, India.
Pacman is an interrupt controller, designed with the concept of priority based selection of peripherals with 16x8 input interrupt lines. The main objective of this Master Thesis is to upgrade 16x8 interrupt controller and priority resolver to 128x8 input interrupt lines and adding a debug feature for this customised processor which has its own instruction set.
In this thesis, the upgradation of Pacman and design of debugging features such as halt, break point, single step are implemented at the Register Transfer Level (RTL) in the processor. The processor is integrated with Memory, JtagtoAHB, System Register modules and the Advanced High-performance Bus (AHB)... (More)
This thesis work was performed at Ineda System Pvt Ltd, Hyderabad, India.
Pacman is an interrupt controller, designed with the concept of priority based selection of peripherals with 16x8 input interrupt lines. The main objective of this Master Thesis is to upgrade 16x8 interrupt controller and priority resolver to 128x8 input interrupt lines and adding a debug feature for this customised processor which has its own instruction set.
In this thesis, the upgradation of Pacman and design of debugging features such as halt, break point, single step are implemented at the Register Transfer Level (RTL) in the processor. The processor is integrated with Memory, JtagtoAHB, System Register modules and the Advanced High-performance Bus (AHB) Arbiter. The functional correctness of the design is verified using system verilog test bench and validated the design in FPGA environment. (Less)
Popular Abstract
Peripheral Access Control Management (Pacman) is a 128x8 Vectored Interrupt Controller designed with the concept of priority based selection of peripherals which requires immediate attention. Debug features such as halt , break point and single step are added to Pacman which gives the user an opportunity to debug this customized processor. AHB Master and Slave are used in the design to communicate with the peripherals on a chip.
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author
Kothamasu, Dinesh LU
supervisor
organization
course
EITM02 20181
year
type
H2 - Master's Degree (Two Years)
subject
keywords
Interrupt Controller and Priority Resolver
report number
LU/LTH-EIT 2018-622
language
English
id
8937956
date added to LUP
2018-04-16 11:23:40
date last changed
2018-04-16 11:23:40
@misc{8937956,
  abstract     = {This thesis work was performed at Ineda System Pvt Ltd, Hyderabad, India.
Pacman is an interrupt controller, designed with the concept of priority based selection of peripherals with 16x8 input interrupt lines. The main objective of this Master Thesis is to upgrade 16x8 interrupt controller and priority resolver to 128x8 input interrupt lines and adding a debug feature for this customised processor which has its own instruction set. 
In this thesis, the upgradation of Pacman and design of debugging features such as halt, break point, single step are implemented at the Register Transfer Level (RTL) in the processor. The processor is integrated with Memory, JtagtoAHB, System Register modules and the Advanced High-performance Bus (AHB) Arbiter. The functional correctness of the design is verified using system verilog test bench and validated the design in FPGA environment.},
  author       = {Kothamasu, Dinesh},
  keyword      = {Interrupt Controller and Priority Resolver},
  language     = {eng},
  note         = {Student Paper},
  title        = {Design of Pacman with Debug Logic},
  year         = {2018},
}