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Spice Circuit Reduction for Speeding up Simulation and Verification

Wang, Menglin LU and Yin, Cancan LU (2019) EITM02 20191
Department of Electrical and Information Technology
Abstract
The focus of this work has been to implement a generic netlist reduction engine to speed up circuit simulations. The netlist reduction techniques are further optimized for Static Random-Access Memory (SRAM), wherein we exploit the repetitive pattern of the circuit.

There are many driving factors for developing a netlist reduction engine for SRAM simulations. In today's System on Chip (SoC), SRAM sizes are in megabyte ranges to support ever-increasing demands for features. The increasing size of SRAM makes it one of the biggest contributors of power consumption and area of a SoC. Many of today's state-of-the-art SoCs have on average more than 50% area and power consumption due to SRAMs. Hence it is very crucial to run full simulations of... (More)
The focus of this work has been to implement a generic netlist reduction engine to speed up circuit simulations. The netlist reduction techniques are further optimized for Static Random-Access Memory (SRAM), wherein we exploit the repetitive pattern of the circuit.

There are many driving factors for developing a netlist reduction engine for SRAM simulations. In today's System on Chip (SoC), SRAM sizes are in megabyte ranges to support ever-increasing demands for features. The increasing size of SRAM makes it one of the biggest contributors of power consumption and area of a SoC. Many of today's state-of-the-art SoCs have on average more than 50% area and power consumption due to SRAMs. Hence it is very crucial to run full simulations of SRAM to check functionality, timing and power numbers. Unfortunately, due to the huge size of SRAM, it is unfeasible to simulate the whole SRAM, since it would take in the order of months to perform simulations. Also, a typical SRAM needs to be run for different corners, which is performed by Monte Carlo simulations, which is even more computationally intensive. Tackling these issues is the key focus of this thesis. We perform this by exploiting the iterative nature of the SRAM circuit.

The design is implemented in Python and verified on Xenergic's latest SRAM by using Cadence simulation tools. The reduction engine has shown to provide a speed up of around 95% (using Spectre simulator) for a 4kb SRAM. Timing deviations of simulation results between the original SRAM netlist and a reduced netlist are below 5%. Furthermore, there is no difference when it comes to SRAM functionality via the digital interface. In addition, time for the whole reduction process is far less than saved simulation time for a large scale circuit. (Less)
Popular Abstract
Nowadays, people’s reliance on electronic products is ever-growing, which is driving the demands for higher computational power and mobility of electronic devices.
This increasing demand has led to quick updates on electronic devices in a very
competitive market, which means time for design cycles in electronic devices can
be very short. Shorter design cycles may help companies seize more opportunities.
IC design takes up a portion of electronics device designs. Hence, the design process of IC needs to be accelerated to adapt to the rapid changes. The simulation
of design plays an important role in the design process. It allows the designer
to know how the design works in reality, so the designer is able to modify and
verify their... (More)
Nowadays, people’s reliance on electronic products is ever-growing, which is driving the demands for higher computational power and mobility of electronic devices.
This increasing demand has led to quick updates on electronic devices in a very
competitive market, which means time for design cycles in electronic devices can
be very short. Shorter design cycles may help companies seize more opportunities.
IC design takes up a portion of electronics device designs. Hence, the design process of IC needs to be accelerated to adapt to the rapid changes. The simulation
of design plays an important role in the design process. It allows the designer
to know how the design works in reality, so the designer is able to modify and
verify their design. However, the simulation can take a huge amount of time, since
circuits today consist of hundreds of thousands of transistors and the transistor
model for running accurate circuit simulation is very complex. This means that a
large amount of data are processed to simulate circuit behavior. Besides, during
the design process, circuit design needs to be modified and verified several times
before manufacturing. Therefore, long simulation time can cause a large increase
in the design time. This master thesis proposes decreasing the simulation time
by ignoring redundant parts of the circuit during the simulation. As a result, the
simulation time of the reduced circuit can be cut significantly while the functionality of the circuit is still ensured. (Less)
Please use this url to cite or link to this publication:
author
Wang, Menglin LU and Yin, Cancan LU
supervisor
organization
course
EITM02 20191
year
type
H2 - Master's Degree (Two Years)
subject
report number
LU/LTH-EIT 2019-698
language
English
id
8981338
date added to LUP
2019-06-17 15:18:08
date last changed
2019-06-17 15:18:08
@misc{8981338,
  abstract     = {{The focus of this work has been to implement a generic netlist reduction engine to speed up circuit simulations. The netlist reduction techniques are further optimized for Static Random-Access Memory (SRAM), wherein we exploit the repetitive pattern of the circuit.

There are many driving factors for developing a netlist reduction engine for SRAM simulations. In today's System on Chip (SoC), SRAM sizes are in megabyte ranges to support ever-increasing demands for features. The increasing size of SRAM makes it one of the biggest contributors of power consumption and area of a SoC. Many of today's state-of-the-art SoCs have on average more than 50% area and power consumption due to SRAMs. Hence it is very crucial to run full simulations of SRAM to check functionality, timing and power numbers. Unfortunately, due to the huge size of SRAM, it is unfeasible to simulate the whole SRAM, since it would take in the order of months to perform simulations. Also, a typical SRAM needs to be run for different corners, which is performed by Monte Carlo simulations, which is even more computationally intensive. Tackling these issues is the key focus of this thesis. We perform this by exploiting the iterative nature of the SRAM circuit.

The design is implemented in Python and verified on Xenergic's latest SRAM by using Cadence simulation tools. The reduction engine has shown to provide a speed up of around 95% (using Spectre simulator) for a 4kb SRAM. Timing deviations of simulation results between the original SRAM netlist and a reduced netlist are below 5%. Furthermore, there is no difference when it comes to SRAM functionality via the digital interface. In addition, time for the whole reduction process is far less than saved simulation time for a large scale circuit.}},
  author       = {{Wang, Menglin and Yin, Cancan}},
  language     = {{eng}},
  note         = {{Student Paper}},
  title        = {{Spice Circuit Reduction for Speeding up Simulation and Verification}},
  year         = {{2019}},
}