RTL power estimation and optimization flow for 5G radio products
(2021) EITM02 20211Department of Electrical and Information Technology
- Abstract
- Power reduction is becoming a critical design requirement for ASIC/SOC designers.
Reducing both dynamic and leakage power is essential to meet power budgets
for portable devices as well as to ensure that these ASICs meet their packaging
and cooling costs. In addition, the power of an ASIC has a significant impact on
its reliability and manufacturing yield.
Also, low-power has become a leading design criterion for 5G Radio products
that demand increasingly higher performance and lower energy footprint. Traditionally, most automated power optimization tools have focused on gate-level and physical level optimizations. However, major power reductions are only possible
by addressing power at the RTL and system levels. At these levels,... (More) - Power reduction is becoming a critical design requirement for ASIC/SOC designers.
Reducing both dynamic and leakage power is essential to meet power budgets
for portable devices as well as to ensure that these ASICs meet their packaging
and cooling costs. In addition, the power of an ASIC has a significant impact on
its reliability and manufacturing yield.
Also, low-power has become a leading design criterion for 5G Radio products
that demand increasingly higher performance and lower energy footprint. Traditionally, most automated power optimization tools have focused on gate-level and physical level optimizations. However, major power reductions are only possible
by addressing power at the RTL and system levels. At these levels, it is possible to make the sequential modifications needed to reduce power and energy consumption
via techniques like sequential clock gating, power gating, frequency scaling, and other micro-architectural techniques.
With the increasing requirement of low power design, estimating power consumption
must be done early in the process and waiting until the netlist is available
can be too late. Designers want to get an accurate power estimate at the RTL stage
to shorten their design period. However, as there is no netlist available at RTL
stage, the accuracy of the power estimated at the RTL stage may not be acceptable.
This thesis begins with a review of several commonly used RTL PE methodologies,
followed by the design of an automated RTL PE flow based on a commercially
available EDA RTL power estimation tool, and finally, a sub-chip for a 5G device
from Ericsson is used as the DUT to investigate the reasons for RTL PE inaccuracy
and ways to improve the accuracies.
The estimated power consumption from this RTL PE flow with and without
calibration is compared with GL PE with front-end netlist and back-end netlist
to identify the critical reason for RTL power estimation inaccuracy, and then a
guideline for improving RTL PE accuracy is listed in the thesis’s result section. (Less) - Popular Abstract
- Nowadays the most advanced chips have a huge amount of transistors, Apple’s M1
chip has about 16 billion transistors,[2]. Nvidia’s RTX 3090 GPU even has 28
billion transistors. According to Moore’s law, the number of transistors in an integrated circuit will double about every two years, which means that in the future, the number of transistors in integrated circuits will get even higher.
With the increase in the number of transistors in integrated circuits, Power consumption has become a big problem. On one hand, high power consumption will
cause huge dissipation of electrical energy, on the other hand, it will also increase the temperature which affects the stability of integrated circuits.
During the design process, the... (More) - Nowadays the most advanced chips have a huge amount of transistors, Apple’s M1
chip has about 16 billion transistors,[2]. Nvidia’s RTX 3090 GPU even has 28
billion transistors. According to Moore’s law, the number of transistors in an integrated circuit will double about every two years, which means that in the future, the number of transistors in integrated circuits will get even higher.
With the increase in the number of transistors in integrated circuits, Power consumption has become a big problem. On one hand, high power consumption will
cause huge dissipation of electrical energy, on the other hand, it will also increase the temperature which affects the stability of integrated circuits.
During the design process, the designer needs to write RTL code according to specification first, then synthesis the RTL code to get the front-end netlist, and after that P&R is done on the front-end netlist in order to get the back-end netlist. it is a very timing-consuming flow. For a big design, the designer spends several months or even several years, in order to complete the flow.
Normally designer can only get the power consumption once the front-end
netlist or back-end netlist is generated, if the power consumption does not meets
the requirement, the designer may need to modify the RTL code and go through the
whole flow again, which will make the whole design time even longer. If designers
can get the power consumption at the RTL stage, time can be saved.
During our thesis work, we want to look into a commercially available EDA
RTL power estimation tool, which aids in the estimation of RTL power. We’ll also
look at how accurate the projected power is at the RTL stage compared to what’s
accessible at the GL PE with front-end netlist, and how we may enhance power
estimation. (Less)
Please use this url to cite or link to this publication:
http://lup.lub.lu.se/student-papers/record/9064675
- author
- Khanna, Divya LU and Zhu, Yu LU
- supervisor
- organization
- course
- EITM02 20211
- year
- 2021
- type
- H2 - Master's Degree (Two Years)
- subject
- keywords
- Power estimation, RTL, gate-level, Power Optimisation
- report number
- LU/LTH-EIT 2021-842
- language
- English
- id
- 9064675
- date added to LUP
- 2021-09-10 12:05:46
- date last changed
- 2021-09-10 12:05:46
@misc{9064675,
abstract = {{Power reduction is becoming a critical design requirement for ASIC/SOC designers.
Reducing both dynamic and leakage power is essential to meet power budgets
for portable devices as well as to ensure that these ASICs meet their packaging
and cooling costs. In addition, the power of an ASIC has a significant impact on
its reliability and manufacturing yield.
Also, low-power has become a leading design criterion for 5G Radio products
that demand increasingly higher performance and lower energy footprint. Traditionally, most automated power optimization tools have focused on gate-level and physical level optimizations. However, major power reductions are only possible
by addressing power at the RTL and system levels. At these levels, it is possible to make the sequential modifications needed to reduce power and energy consumption
via techniques like sequential clock gating, power gating, frequency scaling, and other micro-architectural techniques.
With the increasing requirement of low power design, estimating power consumption
must be done early in the process and waiting until the netlist is available
can be too late. Designers want to get an accurate power estimate at the RTL stage
to shorten their design period. However, as there is no netlist available at RTL
stage, the accuracy of the power estimated at the RTL stage may not be acceptable.
This thesis begins with a review of several commonly used RTL PE methodologies,
followed by the design of an automated RTL PE flow based on a commercially
available EDA RTL power estimation tool, and finally, a sub-chip for a 5G device
from Ericsson is used as the DUT to investigate the reasons for RTL PE inaccuracy
and ways to improve the accuracies.
The estimated power consumption from this RTL PE flow with and without
calibration is compared with GL PE with front-end netlist and back-end netlist
to identify the critical reason for RTL power estimation inaccuracy, and then a
guideline for improving RTL PE accuracy is listed in the thesis’s result section.}},
author = {{Khanna, Divya and Zhu, Yu}},
language = {{eng}},
note = {{Student Paper}},
title = {{RTL power estimation and optimization flow for 5G radio products}},
year = {{2021}},
}