An Approximate Near Data Processing Accelerator for a CNN in a RISC-V Platform
(2022) EITM02 20212Department of Electrical and Information Technology
- Abstract
- In the recent years the world of electronics has faced the fact that Moore's law and Dennard scaling do not describe the progress of performance and integration of integrated circuits anymore. Alongside the costs of reducing the physical dimensions of the transistors another problem that is faced by the current technology is the limited power efficiency and memory bandwidth that results from architectures based on solutions of the past like von Neumann systems. A new trend of alternative architectures capable of increasing the power efficiency and challenge the power and memory wall is emerging with new techniques that target these problems. Near Data Processing, or Near Memory Computation proposes to reduce data latency and power... (More)
- In the recent years the world of electronics has faced the fact that Moore's law and Dennard scaling do not describe the progress of performance and integration of integrated circuits anymore. Alongside the costs of reducing the physical dimensions of the transistors another problem that is faced by the current technology is the limited power efficiency and memory bandwidth that results from architectures based on solutions of the past like von Neumann systems. A new trend of alternative architectures capable of increasing the power efficiency and challenge the power and memory wall is emerging with new techniques that target these problems. Near Data Processing, or Near Memory Computation proposes to reduce data latency and power consumption by bringing the computation as close as possible to the memory. The aim of this Master’s thesis work is to design and implement an Near Data Processing architecture capable of reducing the gap between the computation units and memory bandwidth, improving the overall efficiency of the system. Without dealing with internal memory elements, this Near Data Processing architecture must be able to exploit the integration of memory with computation providing flexibility to enhance data reuse, which is crucial for Neural Network applications. To improve the energy efficiency even further, state of the art approximate multiplier architectures will be studied and an efficient architecture will be utilized within the Neural Network processing units. Advantageously, the approximate computation units can deliver higher efficiency in the system by making a tradeoff between higher power and area efficiency and low accuracy-loss in the fault tolerant Convolutional Neural Network. The implemented Neural Network inference architecture will be based on a Convolutional Neural Network model trained and tested for classification accuracy using the handwritten digits MNIST dataset. The final goal is to design an efficient Near Data Processing unit that can prove high accuracy performances but also be compatible with IoT devices with low energy requirements. (Less)
- Popular Abstract
- Today is the era of big data, as it can be characterized with an unprecedented rate of data generation in different areas such as health care, biology and transportation. Big data analytics require high performance computing platforms which are capable of fast and efficient analysis. Machine learning (ML) and Neural networks (NN) have recently become a popular trend in big data processing due to their versatility in learning from data, creating predictive outcomes and making decisions. ML, being used in a wide range of applications, are shown to be very flexible in implementation and capable of very complex processing tasks with the benefit of having relatively short design and implementation time. Neural Networks carry out a multitude of... (More)
- Today is the era of big data, as it can be characterized with an unprecedented rate of data generation in different areas such as health care, biology and transportation. Big data analytics require high performance computing platforms which are capable of fast and efficient analysis. Machine learning (ML) and Neural networks (NN) have recently become a popular trend in big data processing due to their versatility in learning from data, creating predictive outcomes and making decisions. ML, being used in a wide range of applications, are shown to be very flexible in implementation and capable of very complex processing tasks with the benefit of having relatively short design and implementation time. Neural Networks carry out a multitude of parallel computations with a trained set of parameters, which are required to be stored in memories. Depending on the complexity of the target network, this set of parameters can be large and difficult to manage, which can be interpreted as higher memory footprint and power cost. In this context, it is promising to find and implement new design techniques that aim to reduce the impact that data movement has on nowadays silicon technology, so to make possible to bring complex computation on low power devices such as the ones found in the IoT filed. (Less)
Please use this url to cite or link to this publication:
http://lup.lub.lu.se/student-papers/record/9103536
- author
- Ligas, Dario LU
- supervisor
- organization
- course
- EITM02 20212
- year
- 2022
- type
- H2 - Master's Degree (Two Years)
- subject
- report number
- LU/LTH-EIT 2022-897
- language
- English
- id
- 9103536
- date added to LUP
- 2023-01-25 15:15:21
- date last changed
- 2023-01-25 16:52:53
@misc{9103536,
abstract = {{In the recent years the world of electronics has faced the fact that Moore's law and Dennard scaling do not describe the progress of performance and integration of integrated circuits anymore. Alongside the costs of reducing the physical dimensions of the transistors another problem that is faced by the current technology is the limited power efficiency and memory bandwidth that results from architectures based on solutions of the past like von Neumann systems. A new trend of alternative architectures capable of increasing the power efficiency and challenge the power and memory wall is emerging with new techniques that target these problems. Near Data Processing, or Near Memory Computation proposes to reduce data latency and power consumption by bringing the computation as close as possible to the memory. The aim of this Master’s thesis work is to design and implement an Near Data Processing architecture capable of reducing the gap between the computation units and memory bandwidth, improving the overall efficiency of the system. Without dealing with internal memory elements, this Near Data Processing architecture must be able to exploit the integration of memory with computation providing flexibility to enhance data reuse, which is crucial for Neural Network applications. To improve the energy efficiency even further, state of the art approximate multiplier architectures will be studied and an efficient architecture will be utilized within the Neural Network processing units. Advantageously, the approximate computation units can deliver higher efficiency in the system by making a tradeoff between higher power and area efficiency and low accuracy-loss in the fault tolerant Convolutional Neural Network. The implemented Neural Network inference architecture will be based on a Convolutional Neural Network model trained and tested for classification accuracy using the handwritten digits MNIST dataset. The final goal is to design an efficient Near Data Processing unit that can prove high accuracy performances but also be compatible with IoT devices with low energy requirements.}},
author = {{Ligas, Dario}},
language = {{eng}},
note = {{Student Paper}},
title = {{An Approximate Near Data Processing Accelerator for a CNN in a RISC-V Platform}},
year = {{2022}},
}