Comparative study of ThinLink-based routing optimization

Abstract

In recent decades, advancements in silicon technology have led to a substantial increase in chip complexity, primarily driven by the integration of more transis-tors within a given unit of chip area. Consequently, routing connections between these transistors has emerged as a significant challenge for the physical design of the chips. AMBA’s AXI-4 based connectivity is a commonly employed scheme to connect different segments of a chip. However, the number of wires/connections
that travel between any two chip segments is quite significant and elevate routing congestion. This research dives into the ThinLink-based AXI Interface optimization, specifically harnessing the capabilities of Arm’s TLX-400 Network Interconnect. The core of this study will involve implementing and testing these
optimizations on Ericsson’s existing radio SoC connectivity, which serves as the design under test (DUT) for managing routing congestion. By examining the
effects of this optimization on performance and layout efficiency, the research aims to offer a tangible and actionable solution to counteract routing congestion
challenges in AXI connectivity.
The primary goal of this thesis is to present a solution for optimizing routing congestion within a System-on-Chip (SoC) to enhance area efficiency. The area
factor is pivotal, if the available routing space prove insufficient, adjust the routing channel size becomes necessary, leading to a corresponding changes in die
size and utilization. By addressing congestion, we ensure optimal use of the provided die and channel dimensions, which is critical to achieving the desired
area efficiency. In this study, various channel widths have been evaluated and the resulting performance metrics across different configurations have been com-
pared. This comparison will assist developers in selecting the most appropriate channel width that aligns with specific design requirements.

Popular Abstract

Imagine a bustling city where traffic jams make it difficult to get from one place to another. Now, picture the same problem happening inside a tiny chip in your electronic devices. As technology advances, these chips are packed with more and more transistors, making the pathways between them increasingly congested. This issue, known as routing congestion, can slow down the chip's performance, increase power consumption, and make the overall design process more complicated and expensive.

In the world of chip design, finding efficient ways to manage this congestion is crucial. A recent study conducted by researchers at Lund University, in collaboration with Ericsson, explores an innovative solution using something called the ThinLink-based AXI Interface. This approach aims to optimize the layout of these pathways, ensuring data can travel smoothly and efficiently across the chip.

The study focuses on a specific technology, the TLX-400 Network Interconnect by Arm, which is designed to reduce the number of physical wires needed between different parts of a chip. By doing so, it tackles the congestion problem head-on, similar to how adding more lanes to a highway can alleviate traffic jams. The researchers tested this technology on a radio System-on-Chip (SoC) from Ericsson, which is a type of chip that integrates many functions into one compact unit.

The findings show that by carefully choosing the width of these pathways and strategically placing register slices (components that help manage data flow), they could significantly reduce congestion. This not only improves the chip's performance but also makes better use of the available space, which is crucial for keeping production costs down.

In essence, this study offers a promising solution to one of the most pressing challenges in modern chip design. By optimizing how data routes through the chip, it paves the way for more powerful, efficient, and cost-effective electronic devices. So next time you enjoy a fast, smooth experience on your smartphone or computer, remember that behind the scenes, researchers are constantly innovating to make it all possible.

• author: Shi, Tongying and Darell, Amanda
• supervisor: Per Andersson
• organization: Department of Electrical and Information Technology
• course: EITM02 20241
• year: 2024
• type: H2 - Master's Degree (Two Years)
• subject: Technology and Engineering
• report number: LU/LTH-EIT 2024-975
• language: English
• id: 9162957
• date added to LUP: 2024-06-19 15:42:59
• date last changed: 2024-06-19 15:42:59