Resource Sharing between SoCs through a Dedicated SerDes-channel
(2024) EITM02 20241Department of Electrical and Information Technology
- Abstract
- In modern information technology there is an increase in demand for high-speed communication. Looking at the popular applications of AI and machine learning, a trend is to implement dedicated hardware accelerators for faster and more efficient computing. However this puts more of a demand on the ability to transfer the large amounts of data in the form of weights, input data and results to and from the accelerator.
This sort of system could be realized on a single SoC and a high-speed network with an increasing number of dedicated accelerators and components right on the chip, however two separate SoC leads to more flexibility with only the need to implement a high-speed communication, like the one suggested in this thesis.
In this... (More) - In modern information technology there is an increase in demand for high-speed communication. Looking at the popular applications of AI and machine learning, a trend is to implement dedicated hardware accelerators for faster and more efficient computing. However this puts more of a demand on the ability to transfer the large amounts of data in the form of weights, input data and results to and from the accelerator.
This sort of system could be realized on a single SoC and a high-speed network with an increasing number of dedicated accelerators and components right on the chip, however two separate SoC leads to more flexibility with only the need to implement a high-speed communication, like the one suggested in this thesis.
In this thesis a dedicated high-speed SerDes channel was implemented and verified on two Digilent Nexys4 boards. The implemented physical channel connects the two separate Wishbone buses in their SoCs, allowing for read and writes across SoCs by the channel. The LiteX SoC environment was used as the base for the SoC and AMD Vivado primitives for the physical SerDes implementation. Along with this was the specially designed custom communication protocol, enabling the communication between the Wishbone buses. (Less) - Popular Abstract
- The race for computing power that drives the advancements of popular AI and machine learning applications, such as LLMs like ChatGPT, often relies on dedicated hardware. These performance requirements for speed and efficiency emphasize the need for high-speed data transfers between different components. Whether it is hundreds of high-end GPUs performing inference or clusters with four dedicated accelerators, like those proposed by Yajie Wu et. al. \cite{cite:2x2CNN}, high-speed communication is crucial for making everything work efficiently. A popular high-speed serial link choice and the link used and implemented in this paper is a SerDes channel, which is commonly used in Gigabit Ethernet, PCIe, and other data transmission protocols.
... (More) - The race for computing power that drives the advancements of popular AI and machine learning applications, such as LLMs like ChatGPT, often relies on dedicated hardware. These performance requirements for speed and efficiency emphasize the need for high-speed data transfers between different components. Whether it is hundreds of high-end GPUs performing inference or clusters with four dedicated accelerators, like those proposed by Yajie Wu et. al. \cite{cite:2x2CNN}, high-speed communication is crucial for making everything work efficiently. A popular high-speed serial link choice and the link used and implemented in this paper is a SerDes channel, which is commonly used in Gigabit Ethernet, PCIe, and other data transmission protocols.
High-speed serial data allows for the extension of an existing SoC by incorporating additional SoCs and their resources like larger memory. This enables the storage of weights or data outside the accelerator chip, significantly reducing cost and area, as on-chip memory (such as SRAM) tends to be more expensive and larger in area.
In this thesis an existing SoC structure was modified to include a custom communication protocol over a SerDes channel, allowing read and write operations to be issued on a receiving SoC. This demonstrates the capabilities of a dedicated high-speed SerDes communication channel for resource sharing. The work includes the creation of the physical SerDes channel along with the communication for the Wishbone bus connected to the SoC's CPU.
The proposed implementation proves that resource sharing is possible and promising but some improvements towards the reliability is left for future work. (Less)
Please use this url to cite or link to this publication:
http://lup.lub.lu.se/student-papers/record/9164576
- author
- Vikström, Casper LU and Wang, Kesheng LU
- supervisor
- organization
- course
- EITM02 20241
- year
- 2024
- type
- H2 - Master's Degree (Two Years)
- subject
- keywords
- Serial data communication, SerDes, DMA, SoC, LiteX framework
- report number
- LU/LTH-EIT 2024-988
- language
- English
- id
- 9164576
- date added to LUP
- 2024-06-17 14:03:41
- date last changed
- 2024-06-17 14:03:41
@misc{9164576,
abstract = {{In modern information technology there is an increase in demand for high-speed communication. Looking at the popular applications of AI and machine learning, a trend is to implement dedicated hardware accelerators for faster and more efficient computing. However this puts more of a demand on the ability to transfer the large amounts of data in the form of weights, input data and results to and from the accelerator.
This sort of system could be realized on a single SoC and a high-speed network with an increasing number of dedicated accelerators and components right on the chip, however two separate SoC leads to more flexibility with only the need to implement a high-speed communication, like the one suggested in this thesis.
In this thesis a dedicated high-speed SerDes channel was implemented and verified on two Digilent Nexys4 boards. The implemented physical channel connects the two separate Wishbone buses in their SoCs, allowing for read and writes across SoCs by the channel. The LiteX SoC environment was used as the base for the SoC and AMD Vivado primitives for the physical SerDes implementation. Along with this was the specially designed custom communication protocol, enabling the communication between the Wishbone buses.}},
author = {{Vikström, Casper and Wang, Kesheng}},
language = {{eng}},
note = {{Student Paper}},
title = {{Resource Sharing between SoCs through a Dedicated SerDes-channel}},
year = {{2024}},
}