A 2x Time-Interleaved 24-GS/s 12-Bit Resistive DAC
(2024) EITM02 20241Department of Electrical and Information Technology
- Abstract
- This study evaluates a 12-bit Time-Interleaved (TI) Digital-to-Analog Converter (DAC) operating at 24 GS/s, incorporating Return-to-Zero (RZ) scheming within its sub-DAC cores. Initially, the TI DAC demonstrates superior performance compared to a traditional single-channel DAC. However, the evaluation in this thesis reveals that the TI DAC is more sensitive to timing errors, such as clock skew and duty cycle deviations. While the TI DAC excels in environments where timing precision is maintained, its performance degradation due to timing issues underscores the need for careful management of timing accuracy. Specifically, the study reveals that a 100 fs timing skew results in an SFDR drop to approximately 60 dB, while duty cycle errors of... (More)
- This study evaluates a 12-bit Time-Interleaved (TI) Digital-to-Analog Converter (DAC) operating at 24 GS/s, incorporating Return-to-Zero (RZ) scheming within its sub-DAC cores. Initially, the TI DAC demonstrates superior performance compared to a traditional single-channel DAC. However, the evaluation in this thesis reveals that the TI DAC is more sensitive to timing errors, such as clock skew and duty cycle deviations. While the TI DAC excels in environments where timing precision is maintained, its performance degradation due to timing issues underscores the need for careful management of timing accuracy. Specifically, the study reveals that a 100 fs timing skew results in an SFDR drop to approximately 60 dB, while duty cycle errors of just 0.1% can reduce SFDR to 50 dB. In contrast, when random clock jitter is added, the TI DAC demonstrates comparable SNR performance to the reference DAC. Additionally, performance across various process corners shows the TI-RZ DAC maintaining an SFDR range of 73 dB to 84 dB, superior to the reference DAC, underscoring its robustness against process variations. These findings emphasize the need for effective calibration techniques and careful design considerations to mitigate timing-related issues and enhance DAC performance. (Less)
- Popular Abstract
- Digital-to-Analog Converters (DACs) translate signals from the digital world of computers to the analog world we experience. DACs are essential for transmitting data over networks, creating sound, and even generating images on our screens. But as the demand grows for faster and more reliable data transmission, DACs need to keep up. The solution explored in this research is a special kind of DAC that uses a technique called "Time-Interleaving" to get data from digital to analog at higher rates.
Imagine a store where a single cashier scans items at a fixed pace, limiting how quickly customers can check out. Even as the line grows, the cashier cannot work faster. Now, picture the store adding more checkout lanes, each with a cashier who... (More) - Digital-to-Analog Converters (DACs) translate signals from the digital world of computers to the analog world we experience. DACs are essential for transmitting data over networks, creating sound, and even generating images on our screens. But as the demand grows for faster and more reliable data transmission, DACs need to keep up. The solution explored in this research is a special kind of DAC that uses a technique called "Time-Interleaving" to get data from digital to analog at higher rates.
Imagine a store where a single cashier scans items at a fixed pace, limiting how quickly customers can check out. Even as the line grows, the cashier cannot work faster. Now, picture the store adding more checkout lanes, each with a cashier who works at the same pace but handles a portion of the line. By dividing the workload, the store processes customers much faster overall, even though no individual cashier speeds up.
Similarly, a Time-Interleaved DAC (TI DAC) splits input data across multiple internal "lanes". Each lane operates at a speed that might not be sufficient on its own, but together they achieve much higher rates by processing the data in parallel. This enables TI DACs to overcome the limitations of individual lanes and deliver the performance required for high-frequency applications like wireless communications and high-speed data networks.
As simple as it sounds, TI DACs are not without their challenges. One of the biggest obstacles is something called "interleaving spur", which can disturb the signal if there’s even a tiny mismatch between the lanes. To keep the signal clear, each lane in the DAC must stay perfectly synchronized.
The findings from this study highlight the potential of TI DACs for high speed data conversion. By advancing our understanding of how to control timing errors and minimize interleaving distortions, this work lays the groundwork for even faster and more precise DACs. These advancements are essential for the next generation of wireless communications and high-speed data networks, where maintaining high data rates and signal quality will be critical to performance and connectivity in our increasingly data-driven world. (Less)
Please use this url to cite or link to this publication:
http://lup.lub.lu.se/student-papers/record/9178150
- author
- Zeynalli, Elmidar LU
- supervisor
- organization
- course
- EITM02 20241
- year
- 2024
- type
- H2 - Master's Degree (Two Years)
- subject
- keywords
- Data Converter, DAC, Time Interleaving, TI, Return-to-Zero, RZ
- report number
- LU/LTH-EIT 2024-1031
- language
- English
- id
- 9178150
- date added to LUP
- 2025-02-03 13:14:48
- date last changed
- 2025-02-03 13:14:48
@misc{9178150,
abstract = {{This study evaluates a 12-bit Time-Interleaved (TI) Digital-to-Analog Converter (DAC) operating at 24 GS/s, incorporating Return-to-Zero (RZ) scheming within its sub-DAC cores. Initially, the TI DAC demonstrates superior performance compared to a traditional single-channel DAC. However, the evaluation in this thesis reveals that the TI DAC is more sensitive to timing errors, such as clock skew and duty cycle deviations. While the TI DAC excels in environments where timing precision is maintained, its performance degradation due to timing issues underscores the need for careful management of timing accuracy. Specifically, the study reveals that a 100 fs timing skew results in an SFDR drop to approximately 60 dB, while duty cycle errors of just 0.1% can reduce SFDR to 50 dB. In contrast, when random clock jitter is added, the TI DAC demonstrates comparable SNR performance to the reference DAC. Additionally, performance across various process corners shows the TI-RZ DAC maintaining an SFDR range of 73 dB to 84 dB, superior to the reference DAC, underscoring its robustness against process variations. These findings emphasize the need for effective calibration techniques and careful design considerations to mitigate timing-related issues and enhance DAC performance.}},
author = {{Zeynalli, Elmidar}},
language = {{eng}},
note = {{Student Paper}},
title = {{A 2x Time-Interleaved 24-GS/s 12-Bit Resistive DAC}},
year = {{2024}},
}