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An Analysis of a Novel Ultra-Low Power Receiver

Davill Glas, Elliot LU (2025) EITM01 20251
Department of Electrical and Information Technology
Abstract
Traditionally, radio communication research has focused on improving range and data transmission rates. Over the past decade, there has been a growing demand for small devices that should be able to interact with each other, and to facilitate this growth, low-cost and low-power radios are necessary to ensure devices are able to function for extended periods of time without maintenance. This thesis is focused on analyzing an ultra-low power wake-up receiver operating at 1.95 GHz. The receiver utilizes a mixer-first architecture with a three-phase passive mixer, a ring oscillator locked using a frequency-locked loop (FLL), and a high-gain amplifier chain. The FLL operates on a power budget of only 54 μW, considerably lower than other... (More)
Traditionally, radio communication research has focused on improving range and data transmission rates. Over the past decade, there has been a growing demand for small devices that should be able to interact with each other, and to facilitate this growth, low-cost and low-power radios are necessary to ensure devices are able to function for extended periods of time without maintenance. This thesis is focused on analyzing an ultra-low power wake-up receiver operating at 1.95 GHz. The receiver utilizes a mixer-first architecture with a three-phase passive mixer, a ring oscillator locked using a frequency-locked loop (FLL), and a high-gain amplifier chain. The FLL operates on a power budget of only 54 μW, considerably lower than other state-of-the-art control circuits, with acceptable phase noise levels of -86 dBc/Hz at 10 MHz offset. The receiver is manufactured in 22 nm CMOS and FDSOI technology and occupies 0.47 mm2 of chip area. The entire receiver has an active power consumption of 75 μW and -72 dBm sensitivity. (Less)
Popular Abstract
The Internet of Things (IoT) is the idea that all sorts of objects can talk to the each other. Think of “smart” devices – your wristwatch, home lights, or even a refrigerator that connects to an app. In general, IoT is described as a network of physical devices (from appliances and vehicles to sensors) that collect and share data. They are not just limited to personal products, but IoT devices are also used extensively in various industries. Examples include cars which can measure the distance to other cars and keep a safe distance and driving speed, warehouses which use robots with sensors to find packages instead of workers finding them, and shipping companies where sensors and data analytics find the optimal path to reduce fuel... (More)
The Internet of Things (IoT) is the idea that all sorts of objects can talk to the each other. Think of “smart” devices – your wristwatch, home lights, or even a refrigerator that connects to an app. In general, IoT is described as a network of physical devices (from appliances and vehicles to sensors) that collect and share data. They are not just limited to personal products, but IoT devices are also used extensively in various industries. Examples include cars which can measure the distance to other cars and keep a safe distance and driving speed, warehouses which use robots with sensors to find packages instead of workers finding them, and shipping companies where sensors and data analytics find the optimal path to reduce fuel consumption.

This shift in our ability to set up networks of sensors is driven by the continued innovations and improvements to radio communication systems. Each connected device needs a radio to communicate and listen to other devices. Research has greatly improved the reliability, range, and power efficiency of radios, which means that IoT devices can be cheaper and last longer. Power consumption is especially important for sensor networks where maintenance is difficult or impossible, which means devices might have to operate with a small battery for up to years without running out of power.

This work is focused on improving the existing solutions for low-power radios, by analyzing a novel radio and benchmarking against other published radios. Specifically, it looks at a wake-up receiver, whose job is to detect a wake-up code whereby it can wake-up a more powerful radio to receive the rest of the data. The wake-up receivers job is to receive the wake-up signal, strengthen the wanted signal and suppressing unwanted noise, bring it down to a lower frequency, and check if the received signal matches the expected signal.

Operating on high frequencies is expensive in terms of power, so the challenge becomes to minimize the power consumption of the circuit while still maintaining acceptable sensitivity and tolerance to noise. The analyzed receiver operates at 1.95 GHz, and has a power consumption of just 75 μW thanks to a frequency stabilizing circuit with unusually low power consumption, at a data rate of 5 kbps. (Less)
Please use this url to cite or link to this publication:
author
Davill Glas, Elliot LU
supervisor
organization
course
EITM01 20251
year
type
H2 - Master's Degree (Two Years)
subject
report number
LU/LTH-EIT 2025-1054
language
English
id
9196708
date added to LUP
2025-06-11 13:35:47
date last changed
2025-06-11 13:35:47
@misc{9196708,
  abstract     = {{Traditionally, radio communication research has focused on improving range and data transmission rates. Over the past decade, there has been a growing demand for small devices that should be able to interact with each other, and to facilitate this growth, low-cost and low-power radios are necessary to ensure devices are able to function for extended periods of time without maintenance. This thesis is focused on analyzing an ultra-low power wake-up receiver operating at 1.95 GHz. The receiver utilizes a mixer-first architecture with a three-phase passive mixer, a ring oscillator locked using a frequency-locked loop (FLL), and a high-gain amplifier chain. The FLL operates on a power budget of only 54 μW, considerably lower than other state-of-the-art control circuits, with acceptable phase noise levels of -86 dBc/Hz at 10 MHz offset. The receiver is manufactured in 22 nm CMOS and FDSOI technology and occupies 0.47 mm2 of chip area. The entire receiver has an active power consumption of 75 μW and -72 dBm sensitivity.}},
  author       = {{Davill Glas, Elliot}},
  language     = {{eng}},
  note         = {{Student Paper}},
  title        = {{An Analysis of a Novel Ultra-Low Power Receiver}},
  year         = {{2025}},
}