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A 10-bit Linear Interpolation DAC with Tree-structured DEM for WiFi 6 Application

Zeng, Wenxuan LU (2025) EITM02 20251
Department of Electrical and Information Technology
Abstract
This thesis focuses on two primary parts: the design of a 10-bit medium high-speed, high-linearity current-steering digital-to-analog converter (DAC), and the implementation of a linear analog interpolation technique aimed at suppressing images at the DAC output.

Design considerations for the current-steering DAC are discussed comprehensively, and the circuit is designed in 22nm Fully-Depleted Silicon-On-Insulator (FDSOI) CMOS technology. A tree-structured Dynamic Element Matching (DEM) scheme is employed to mitigate nonlinearity arising from current source mismatch. The principles and circuit implementation of DEM are analyzed in detail. To replace the conventional low-pass filter (LPF) typically used after the DAC in transmitters, a... (More)
This thesis focuses on two primary parts: the design of a 10-bit medium high-speed, high-linearity current-steering digital-to-analog converter (DAC), and the implementation of a linear analog interpolation technique aimed at suppressing images at the DAC output.

Design considerations for the current-steering DAC are discussed comprehensively, and the circuit is designed in 22nm Fully-Depleted Silicon-On-Insulator (FDSOI) CMOS technology. A tree-structured Dynamic Element Matching (DEM) scheme is employed to mitigate nonlinearity arising from current source mismatch. The principles and circuit implementation of DEM are analyzed in detail. To replace the conventional low-pass filter (LPF) typically used after the DAC in transmitters, a four-fold analog linear interpolation technique in conjunction with an RC filter is proposed. This approach effectively attenuates images to meet system requirements. The theory and feasibility of linear interpolation are thoroughly discussed.

At a sampling rate of 128MHz and an input signal frequency of 10MHz, the interpolated DAC achieves 800mV peak-to-peak output swing, an Effective Number of Bits (ENOB) of 9.63 bits, a Spurious-Free Dynamic Range (SFDR) of 72.7dB, and a maximum image level of –48.7dBc under typical process corner, at 50◦C and 0.83V supply voltage. The DAC core consumes an average current of 2.13mA. (Less)
Please use this url to cite or link to this publication:
author
Zeng, Wenxuan LU
supervisor
organization
course
EITM02 20251
year
type
H2 - Master's Degree (Two Years)
subject
report number
LU/LTH-EIT 2025-1091
language
English
id
9211883
date added to LUP
2025-09-08 10:17:08
date last changed
2025-09-08 10:17:08
@misc{9211883,
  abstract     = {{This thesis focuses on two primary parts: the design of a 10-bit medium high-speed, high-linearity current-steering digital-to-analog converter (DAC), and the implementation of a linear analog interpolation technique aimed at suppressing images at the DAC output.

Design considerations for the current-steering DAC are discussed comprehensively, and the circuit is designed in 22nm Fully-Depleted Silicon-On-Insulator (FDSOI) CMOS technology. A tree-structured Dynamic Element Matching (DEM) scheme is employed to mitigate nonlinearity arising from current source mismatch. The principles and circuit implementation of DEM are analyzed in detail. To replace the conventional low-pass filter (LPF) typically used after the DAC in transmitters, a four-fold analog linear interpolation technique in conjunction with an RC filter is proposed. This approach effectively attenuates images to meet system requirements. The theory and feasibility of linear interpolation are thoroughly discussed.

At a sampling rate of 128MHz and an input signal frequency of 10MHz, the interpolated DAC achieves 800mV peak-to-peak output swing, an Effective Number of Bits (ENOB) of 9.63 bits, a Spurious-Free Dynamic Range (SFDR) of 72.7dB, and a maximum image level of –48.7dBc under typical process corner, at 50◦C and 0.83V supply voltage. The DAC core consumes an average current of 2.13mA.}},
  author       = {{Zeng, Wenxuan}},
  language     = {{eng}},
  note         = {{Student Paper}},
  title        = {{A 10-bit Linear Interpolation DAC with Tree-structured DEM for WiFi 6 Application}},
  year         = {{2025}},
}