Chain characterisation of sub-circuits for the study of SRAM

Abstract

Characterising the performance of ICs is a daunting task. With every year that passes, transistor technology keeps advancing and reducing in size. We are at a moment where, due to working with sub-90nm processes, it is not possible to have complete control over the manufacturing of the chips on the silicon wafers. It is mandatory to characterise the behaviour of each transistor using statistics, namely probability density functions. When designing integrated circuits, it is necessary to simulate them in order to be able to check behaviour, performance, power estimations, ageing, etc. Simulations of large and complex systems require a lot of time and computing power, which in a fast paced environment like the micro-electronics world might not always be on hand.

There is a need to improve simulation times to save time and gain precision, because every simulation that is not done because of time is a performance, a reliability, or an opportunity for improvement lost. Simulations must account for the variations observed in the LVF models. That means that to characterise a circuit we need several hundreds or thousands of iterations.

This project aims to create a prediction of the timing in SRAM circuits. For this, it divides the SRAM in different blocks depending on their functionality, studies the statistical timings of each one of those sub-blocks and then it adds the contributions in a mathematical model.

In this research, we explore the relationship between the input signal of a circuit block and the output signal. The output can be characterised statistically. When we have several blocks, we can create a chain of circuits by adding the distributions mathematically, without the need of an intermediate simulation that contains all blocks. This allows for a faster prediction of the performance of the SRAM circuit. As each block is now characterised, if later some changes one the design of one or a few blocks, there is no need to rerun the simulations of the complete circuit. It simply requires to change the liberty data of the block and recalculate the contributions in the chain, saving time and power while not losing noticeable precision.

Popular Abstract

Memories are an electronic device that stores information used for later retrieval. The memories of electronic devices can be thought of as the memory that we humans have, albeit in a vastly different form. With the advancement of technology, memory chips have increased their capacity, performance, and efficiency, while greatly reducing the actual size of the device. This fascinating advancement in technology has led to extremely complicated circuit designs inside the memory chip.

Memories in current electronic systems such as those found on a smartphone are an enormous bottleneck of the overall performance of the device. In addition, memory use intensifies with increasing data flow in our devices. Simply comparing the evolution of the sizes of different PC operative systems, we observe that Windows XP was merely 1.5 Gigabytes of disk space, while the current Windows 11 after installation is more than 24 Gigabytes, just 20 years later. But not only the OS, the images have grown in size, audio files, and all the programmes.

Memory is not only used to store long-term data. Some of it also has to be used temporarily while the programme is running. There must be different types of memory for each use case. For the common reader to understand, you can think of it as follows. The memory contents are inside books. The books are stored in a big long-term memory, which is your library. However, when you are studying a particular subject, you can only keep a fixed and small amount of books on your desk, your short-term memory. This short-term memory needs to be very fast to keep up with the processor speed, referring back to the analogy, which would be the readers’ brain. You would not like to have to go to the big shelf and find the book every time. This short term memory is RAM in computers.

Memories’ circuitry is of extreme complexity. There are many different subcircuits in charge of different tasks. To understand how the performance of the memory is, we must understand how each of the circuits behave. In simpler words, to measure the performance of a memory, we must be able to estimate the delay between the request of data from our input signal and the delivery of such data in the output. What this thesis aims to do is estimate the performance of the memory chip by addressing each subcircuit individually and estimating how each one contributes towards the overall performance. In particular, we focus on a volatile type of memory, an SRAM memory. This method should be faster and less computing intensive than analysing the complete memory system as a whole.

• author: Barba García, Carlos
• supervisor: Pietro Andreani
• organization: Department of Electrical and Information Technology
• course: EITM02 20251
• year: 2025
• type: H2 - Master's Degree (Two Years)
• subject: Technology and Engineering
• keywords: SRAM, statistical analysis, timing analysis, Monte Carlo simulations
• report number: LU/LTH-EIT 2025-1093
• language: English
• id: 9212200
• date added to LUP: 2025-09-29 13:48:59
• date last changed: 2025-09-29 13:48:59