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- 2017
-
Mark
List Decoding of Polar Codes
(
- Master (Two yrs)
-
Mark
Energy Consumption and Light Interference Study for the Concept Smart Mirror
(
- Master (Two yrs)
- 2016
-
Mark
High speed backbone for FPGA at ESS
(
- Master (Two yrs)
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Mark
Commissioning and Characterization of Two Undulators at the MAX IV 3 GeV Storage Ring
(
- Master (Two yrs)
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Mark
Prototype for Measurement Tools for Evaluating the Crusher Feed using Digital Signal Processing
(
- Master (Two yrs)
-
Mark
TEM Cell design for Material Characterization
(
- Master (Two yrs)
-
Mark
Turbo Decoder with early stopping criteria
(
- Master (Two yrs)
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Mark
Modeling and Implementation of A 6-Bit, 50MHz Pipelined ADC in CMOS
(
- Master (Two yrs)
-
Mark
The Design and Linearization of 60GHz Injection Locked Power Amplifier
(
- Master (Two yrs)
-
Mark
Studies of vacuum discharges in the CLIC accelerating structure
(
- Master (Two yrs)