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Hardware Implementation of the Logarithm Function using Improved Parabolic Synthesis

Lai, Jingou (2013) EITM01 20131
Department of Electrical and Information Technology
Abstract
This thesis presents a design that approximates the fractional part of the based two
logarithm function by using Improved Parabolic Synthesis including its CMOS
VLSI implementations. Improved Parabolic Synthesis is a novel methodology in
favor of implementing unary functions e.g. trigonometric, logarithm, square root
etc. in hardware. It is an evolved approach from Parabolic Synthesis by combining
it with Second-Degree Interpolation. In the thesis, the design explores a simple
and parallel architecture for fast timing and optimizes wordlengths in computing
stages for a small design. The error behavior of the design is described and char-
acterized to meet the desired error metrics. This implementation is compared to
other... (More)
This thesis presents a design that approximates the fractional part of the based two
logarithm function by using Improved Parabolic Synthesis including its CMOS
VLSI implementations. Improved Parabolic Synthesis is a novel methodology in
favor of implementing unary functions e.g. trigonometric, logarithm, square root
etc. in hardware. It is an evolved approach from Parabolic Synthesis by combining
it with Second-Degree Interpolation. In the thesis, the design explores a simple
and parallel architecture for fast timing and optimizes wordlengths in computing
stages for a small design. The error behavior of the design is described and char-
acterized to meet the desired error metrics. This implementation is compared to
other approaches e.g. Parabolic Synthesis and CORDIC using 65nm standard cell
libraries and it is proved to have better performance in terms of smaller chip area,
lower dynamic power, and shorter critical path. (Less)
Please use this url to cite or link to this publication:
author
Lai, Jingou
supervisor
organization
course
EITM01 20131
year
type
H2 - Master's Degree (Two Years)
subject
report number
Rappoert 350
language
English
id
8052090
date added to LUP
2015-10-06 09:49:44
date last changed
2015-10-06 09:49:46
@misc{8052090,
  abstract     = {{This thesis presents a design that approximates the fractional part of the based two
logarithm function by using Improved Parabolic Synthesis including its CMOS
VLSI implementations. Improved Parabolic Synthesis is a novel methodology in
favor of implementing unary functions e.g. trigonometric, logarithm, square root
etc. in hardware. It is an evolved approach from Parabolic Synthesis by combining
it with Second-Degree Interpolation. In the thesis, the design explores a simple
and parallel architecture for fast timing and optimizes wordlengths in computing
stages for a small design. The error behavior of the design is described and char-
acterized to meet the desired error metrics. This implementation is compared to
other approaches e.g. Parabolic Synthesis and CORDIC using 65nm standard cell
libraries and it is proved to have better performance in terms of smaller chip area,
lower dynamic power, and shorter critical path.}},
  author       = {{Lai, Jingou}},
  language     = {{eng}},
  note         = {{Student Paper}},
  title        = {{Hardware Implementation of the Logarithm Function using Improved Parabolic Synthesis}},
  year         = {{2013}},
}