InAs and high-k oxides, a scanning tunnelling study of their interfaces

Abstract

In order for semiconductor materials to be suitable for implementation in new and progressive devices they have to be of better electronic characteristics than currently used materials, and maintain these once treated and put into action. It is important to verify that bulk characteristics are not hindered at the surface when a given semiconductor is put in contact with another material due to necessity. In particular, one may want to isolate the surface of a semiconductor from the ambient, and implement artificially grown insulators, such as some types of oxides, to do just this. It is then crucial to verify that the semiconductor’s value is not compromised by it being put into contact with the insulator.

III-V semiconductors are very promising, in terms of electronic characteristics, when it comes to application in progressive devices. However, they are known to have defect-rich native oxides, which means that a number of different surface treatment techniques are required to replace them with better ones and ultimately allow for III-V implementation. Moreover, one has to make sure that interface quality between III-V semiconductors and artificially grown oxides is appropriate.

In this project, InAs (one of many III-V semiconductors) surfaces are considered, alongside the interfaces between them and thin HfO2 (hafnium oxide, a highly insulating material) layers. Sample preparation is realised through annealing (under atomic hydrogen flow) for surface cleaning, and atomic layer deposition (ALD) for controlled deposition of insulating oxide. The main tools at hand for sample analysis consist in scanning tunnelling microscopes, hence the use of scanning tunnelling microscopy (STM) and scanning tunnelling spectroscopy (STS) to record data. All in all, it is deduced that electron states altering the standard InAs band structure are at times present at the interface between semiconductor and oxide, hinting at creation of imperfect samples. Nevertheless, the work carried out in this project should open the door for further investigation on what materials and laboratory procedures work best and will eventually meet optimal interface conditions.

Popular Abstract

Electronic devices are essential to our everyday life, and what allows them to improve over time is in big part the semiconductor industry, which goes hand in hand with the production and clustering of transistors. These can be pictured as tiny switches, operating between states of current flowing and not flowing through them, which are at the base of data processing. For there to be current flow in a transistor, a bias must be applied onto a semiconductor channel connecting two contacts: the source and the drain. This is applied thanks to a third component, the gate, which must be separated from the channel by a highly insulating material to avoid signal loss. Silicon is by far the most implemented semiconductor material. Why it is so? Are there any candidates that could outperform silicon if implemented in its place?

Other semiconductor materials, such as III-Vs (alloys of elements from the third and fifth column of the periodic table), present better electronic properties than silicon itself, and seem like a perfect alternative. Of course there is more to account for, as the semiconductor channel is but one of the components in a transistor. Another important factor is the (insulating) oxide layer that separates the gate from the semiconductor. If this is of poor quality, the transistor as a whole is compromised. This is where silicon excels as its native oxide is well behaved, meaning that once a silicon object is grown in the laboratory, it can promptly be implemented in device engineering. This is not the case for other semiconductors, as their native oxides alter surface electronic properties and have to be replaced by other (less invasive) insulators. How can one find the right substitute? How should it be treated? How can it outperform silicon and yet be found in an accessible price range?

To answer the above questions one should perform a careful study of a candidate at the surface level, i.e. where impurities and native oxides collect, and evaluate necessary surface cleaning techniques (to remove them) and deposition techniques (replace them with desired insulators). This is where my work comes in play, none other than the review of indium-arsenide alloys (InAs, a III-V semiconductor) at the surface level, and at the interface with artificially deposited oxides. Scanning tunneling microscopy, which grants resolution up to the atomic scale, and spectroscopy, which gives the possibility to characterize electron density at given energies, are the tools at hand.

It is found that interface states are at times present between InAs and artificially deposited insulators, meaning that electronic features of the semiconductor are somewhat altered by it being in contact with another material, even if the latter is deposited following appropriate laboratory procedures. On the other hand, treated surfaces present improved conditions when compared to untreated ones, and sample successfulness seems to rely on specific superficial features that arise from having different surface terminations and orientations. Additional effort put into perfecting laboratory procedures is likely to yield better and better samples. How can there be future in electronics if devices are forced to rely on outdated technologies? How will industries cope with the impossibility to provide new products as they would at best slightly outperform their predecessors? These seem like questions that do not affect our current society. However, they will most likely play a role in determining where research at the nanoscale will be heading in the future, and it would be best if by then some resources had already been put into the matter.

• author: Åstrand, Mattias
• supervisor: Rainer Timm; Andrea Troian
• organization: Synchrotron Radiation Research; Department of Physics
• course: FYSK02 20181
• year: 2018
• type: M2 - Bachelor Degree
• subject: Physics and Astronomy
• keywords: Semiconductor, High-k, Atomic layer deposition, Scanning tunnelling microscopy, Scanning tunnelling spectroscopy
• language: English
• id: 8954289
• date added to LUP: 2018-07-10 18:37:04
• date last changed: 2018-07-10 18:37:04