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Investigation of Resistive Random Access Memory for 1T1R Nanowire Array Integration

Theodoridis, Orestes LU (2020) FYSM30 20201
Solid State Physics
Department of Physics
Abstract
As modern electronics have started to reach its physical scaling limits, novel architectures and physics is needed to meet future demands. Oxide-based Resistive Random Access Memory (RRAM) is a new emerging technology that uses filament formation and rupture in thin oxides to generate resistive switching. Structure of RRAM devices often use transistors as selector devices. In this work a one-transistor-one-RRAM (1T1R) device is characterised using pulsed measurements. The endurance of the device is extracted as well as the switching probability. Moreover, the data acquired from the device is used to simulate 1T1R nano-wire (NW) arrays by integrating a cell level small signal model with an array-level model. Analytical expressions are used... (More)
As modern electronics have started to reach its physical scaling limits, novel architectures and physics is needed to meet future demands. Oxide-based Resistive Random Access Memory (RRAM) is a new emerging technology that uses filament formation and rupture in thin oxides to generate resistive switching. Structure of RRAM devices often use transistors as selector devices. In this work a one-transistor-one-RRAM (1T1R) device is characterised using pulsed measurements. The endurance of the device is extracted as well as the switching probability. Moreover, the data acquired from the device is used to simulate 1T1R nano-wire (NW) arrays by integrating a cell level small signal model with an array-level model. Analytical expressions are used to calculate parasitic capacitances. Worst-case cell analyses of the access voltage and read margin are performed for different pulse widths, resistivities and technology nodes. The average switching probabilities for a given array size are also calculated using experimental data. It turns out that the examined device showed excellent endurance, exceeding 2 million cycles. Moreover, it also showed excellent switching characteristics and resistance window. Simulations showed that high probability of switching could be achieved even for array sizes > 1000 bits. These results show that it is possible to integrate > Mbit sub-arrays with low-voltage 10 ns pulses, providing a foundation for larger Gbit memory sizes, which are comparable with current DRAM and NAND technology. (Less)
Popular Abstract
Knowledge, science and ultimately society would be impossible, were it not for memory. While we are normally used to thinking of memory as an inherently cerebral concept and can seem to belong within the domain of psychology, it is also a technology that has evolved dramatically throughout the history of humanity. Early tribes used cave paintings, in ancient Egypt and Greece papyrus was invented to pass on information. As history progressed, electromagnetism was discovered and as such magnetic tapes, capacitors and silicon transistors are used today to hold the vast majority of information, in the form of hard drive disks, solid state drives and USB sticks. The transistors and capacitors of today have been scaled down to a few tenths of... (More)
Knowledge, science and ultimately society would be impossible, were it not for memory. While we are normally used to thinking of memory as an inherently cerebral concept and can seem to belong within the domain of psychology, it is also a technology that has evolved dramatically throughout the history of humanity. Early tribes used cave paintings, in ancient Egypt and Greece papyrus was invented to pass on information. As history progressed, electromagnetism was discovered and as such magnetic tapes, capacitors and silicon transistors are used today to hold the vast majority of information, in the form of hard drive disks, solid state drives and USB sticks. The transistors and capacitors of today have been scaled down to a few tenths of nanometers, giving a high speed and high density of memory.

The future holds many challenges. One of them is the scaling of electrical components. When they are scaled down enough (in the order of a few nanometers) quantum effects will inhibit their function. The speed and size of the today’s components are thus seen as having reached their limits. Another challenge has to do with memory applications, in particular the architecture of a computer. In conventional architectures, the memory and processing of information is separated. Imagine if you have a calculator, but, for some reason also have lost your way of recollecting numbers. Every time you want to compute a number you have to wait for your friend, who has excellent memory, to call you on the phone to tell you what to type on the calculator. After a while it would be rather tiresome if you would have to calculate, say, three digits per second. Your friend, your phone and your responsivity would have to be really fast. It would, in the end, be a lot easier if you had all the numbers noted next to you. This is the situation of a modern computer, although a billion times faster.

These two bottlenecks of current memory technology motivates novel architectures for faster, smaller and ultimately more energy efficient technology. One of the emerging technologies, which holds promise to solve both of these challenges, is called Resistive Random Access Memory (RRAM) or resistive switches. This component is built like a capacitor, but works much like a resistor. The construction is simple: an oxide is sandwiched between two metals. Scientists have realised that a capacitor with the correct materials can be pulsed to form or rupture a filament in the oxide, which in turn conducts current. A formed filament allows for a large current to flow, while a ruptured filament allows for a small current. With this simple mechanism the RRAM device can work as a switch as well as a holder of memory.
The mechanisms of RRAM in turn means that the RRAM can function as an artificial neuron, making it an attractive technology for artificial intelligence. Is it possible to build a brain? In order to begin considering this, RRAM devices need to be constructed on arrays. An RRAM array is simply a square grid with a RRAM device at each intersection. To operate a device, you need its address, which for simplicity is a column and a row of the array. The selected devices can be probed by a small pulse. The current it gives off tells you if it is in a high resistive state (a logical 0) or in a low resistive state (a logical 1). For large pulses the device is switched from a 0 to a 1 or vice versa.

One problem that arises in arrays is the pulse strength. The further into the array a pulse travels, the less information it carries, thanks to unwanted inhibitors (parasitic elements) of the array. You can think of an array as a giant maze. Your objective is to carry a number of glass marbles in your hands to a destination, where your memory genius friend is waiting. Your path is long and the constituted by soil and mud. Naturally you will get tired and, clumsy as you are, drop some marbles along the way. It is clear that the longer you have to run, the more marbles will fall and, ultimately, you will be out of marbles. In the same way, for large enough arrays, there will be no information to reach the RRAM cell. Another problem has to do with unintentional switching. When you send a pulse, how can you control unintentional switching? Modern solutions include additional components, such as diodes or transistors. This work uses nano-wire transistors, which are essentially small pillars, a few hundred of nanometers high and a few tenths of nanometers in diameter.
For RRAM arrays both of these situations need some investigation. How large can an array be reliably operated? What types of parasitic elements inhibit information flow? What are the probabilities of switching a RRAM device? How many times can you operate an RRAM before it fails to function? These type of questions have been examined in this work. For a device this project has showed that it can be operated on several million times before failing. Moreover, RRAM devices show excellent performance in array environments. It was shown that, indeed, nano-wire RRAM arrays can be quite large. As a result, RRAM technology stands as a valid contender for future electronics. (Less)
Please use this url to cite or link to this publication:
author
Theodoridis, Orestes LU
supervisor
organization
course
FYSM30 20201
year
type
H2 - Master's Degree (Two Years)
subject
keywords
RRAM, Nanowire, Memory Technology, Nanoelectronics, Nanoscience
language
English
id
9011673
date added to LUP
2020-06-02 11:52:59
date last changed
2020-06-02 11:52:59
@misc{9011673,
  abstract     = {{As modern electronics have started to reach its physical scaling limits, novel architectures and physics is needed to meet future demands. Oxide-based Resistive Random Access Memory (RRAM) is a new emerging technology that uses filament formation and rupture in thin oxides to generate resistive switching. Structure of RRAM devices often use transistors as selector devices. In this work a one-transistor-one-RRAM (1T1R) device is characterised using pulsed measurements. The endurance of the device is extracted as well as the switching probability. Moreover, the data acquired from the device is used to simulate 1T1R nano-wire (NW) arrays by integrating a cell level small signal model with an array-level model. Analytical expressions are used to calculate parasitic capacitances. Worst-case cell analyses of the access voltage and read margin are performed for different pulse widths, resistivities and technology nodes. The average switching probabilities for a given array size are also calculated using experimental data. It turns out that the examined device showed excellent endurance, exceeding 2 million cycles. Moreover, it also showed excellent switching characteristics and resistance window. Simulations showed that high probability of switching could be achieved even for array sizes > 1000 bits. These results show that it is possible to integrate > Mbit sub-arrays with low-voltage 10 ns pulses, providing a foundation for larger Gbit memory sizes, which are comparable with current DRAM and NAND technology.}},
  author       = {{Theodoridis, Orestes}},
  language     = {{eng}},
  note         = {{Student Paper}},
  title        = {{Investigation of Resistive Random Access Memory for 1T1R Nanowire Array Integration}},
  year         = {{2020}},
}