Department of Electrical and Information Technology
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- 2021
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Mark
Real-time Scheduling in Datacentre Clusters
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- Master (Two yrs)
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Mark
Customization of Ibex RISC-V Processor Core
2021) In Customization of Ibex RISC-V Processor Core EITM02 20211(
Department of Electrical and Information Technology- Master (Two yrs)
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Mark
Energy efficient Ericsson Many-Core Architecture (EMCA) IP blocks for 5G ASIC
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- Master (Two yrs)
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Mark
RTL power estimation and optimization flow for 5G radio products
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- Master (Two yrs)
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Mark
Converting Hardware to a Container Solution and its Security Implication
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- Master (Two yrs)
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Mark
Design parameterizable filter using High Level Synthesis
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- Master (Two yrs)
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Mark
Power analysis on FPGA implementation of Classic McEliece
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- Master (Two yrs)
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Mark
Automating vulnerability remediation in Maven
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- Master (Two yrs)
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Mark
A Study on Efficient Memory Utilization in Machine Learning and Memory Intensive Systems
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- Master (Two yrs)
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Mark
On-chip Instrument Access Through System Hierarchy
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- Master (Two yrs)