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DLL Based Reference Multiplier for the use in a PLL for WLAN applications

Gupta, Kamal LU (2015) FYSM31 20141
Department of Physics
Abstract (Swedish)
This master’s thesis project report deals with the design of multiplier for the reference signal to the Phase Locked Loop (PLL) used in WLAN application. The reference multiplier designed is based on a newly proposed architecture of dual loop feedback Delay Locked Loop (DLL) in which multiplication is performed within the loops. To lock the DLL, input signal is required to be delayed only for three by eighth of the period of input reference signal. The linear tuning range of the inverter-based voltage control delay line (VCDL) has been extended by making minimal modification in the circuit. Introduced VCDL shows good phase noise performance as less number of delay units are used due to wider delay range. The effect of reference... (More)
This master’s thesis project report deals with the design of multiplier for the reference signal to the Phase Locked Loop (PLL) used in WLAN application. The reference multiplier designed is based on a newly proposed architecture of dual loop feedback Delay Locked Loop (DLL) in which multiplication is performed within the loops. To lock the DLL, input signal is required to be delayed only for three by eighth of the period of input reference signal. The linear tuning range of the inverter-based voltage control delay line (VCDL) has been extended by making minimal modification in the circuit. Introduced VCDL shows good phase noise performance as less number of delay units are used due to wider delay range. The effect of reference multiplier’s jitter and spurs on the PLL’s performance has been analyzed. The circuit has been implemented in 55 nm CMOS technology from Global Foundry. For 160 MHz output signal, simulated results show an average of 4.5 dBc/Hz improvement in phase noise throughout the offset frequencies with the output jitter of 6 ps and dynamic current consumption of 2.767 mA (Less)
Popular Abstract
Kamal Kumar Gupta

DLL Based Reference Multiplier for the use in a PLL for WLAN applications
In modern wireless communication system, a frequency synthesizer/multiplier is one of the main building blocks of the system. For on-chip application, a frequency synthesizer is used as local oscillator (LO) to generate precise frequency from a single base frequency source, usually a crystal oscillator. The conventional and most famous way of implementing on chip LO to generate radio frequency (RF) is using Phase Locked Loop (PLL). The overall performance of the communication system depends upon the PLL therefore its performance parameters including phase noise and spurs power level are very critical.
To satisfy the ever growing demand of high... (More)
Kamal Kumar Gupta

DLL Based Reference Multiplier for the use in a PLL for WLAN applications
In modern wireless communication system, a frequency synthesizer/multiplier is one of the main building blocks of the system. For on-chip application, a frequency synthesizer is used as local oscillator (LO) to generate precise frequency from a single base frequency source, usually a crystal oscillator. The conventional and most famous way of implementing on chip LO to generate radio frequency (RF) is using Phase Locked Loop (PLL). The overall performance of the communication system depends upon the PLL therefore its performance parameters including phase noise and spurs power level are very critical.
To satisfy the ever growing demand of high speed data in WLAN and cellular telephony systems, high performance on-chip LO frequency synthesizer is required. Phase noise is the most common parameter for the characterization of frequency synthesizers in the frequency domain. Minimizing the phase noise and spurs while satisfying other specifications of frequency synthesizer have always been a great challenge in RF design. One of the fundamental limitations to the PLL design is the frequency division ratio from the Voltage Control Oscillator (VCO) output to the comparison frequency input. The PLL division ratio (N) is the main parameter that defines the transfer function for the different noise contributors of the PLL to the output phase noise of the VCO. The lower the value of N the better the phase noise. To lower the N, higher comparison or reference frequency is required. Higher comparison frequency can be achieved with a higher frequency crystal oscillator. However, high frequency crystals can become expensive and difficult to use for designing the on-chip LOs. An interesting alternative would therefore be to multiply the reference frequency prior to the PLL input. Recently various works have been done in this direction that use different low noise reference frequency multipliers like Delay Locked Loop (DLL) or other techniques to lower the PLL division ratio.
This master thesis project deals with the design of a multiplier for the reference signal to the PLL used in WLAN application. The reference multiplier designed is based on newly proposed architecture of dual loop feedback DLL in which multiplication is performed within the loops. To lock the DLL, the input signal is required to be delayed only for three by eighth period of the input reference signal. The linear tuning range of the invertor based voltage control delay line (VCDL) has been extended by making a minimal modification in the circuit. The introduced VCDL shows good phase noise performance as less number of delay units are used due to wider delay range. The effect of the jitter and the spurs of the reference multiplier on the performance of the PLL has been analyzed. The circuit has been implemented in 55nm CMOS technology from Global Foundry. The simulated results show average of 4.5dBc/Hz improvement in phase noise throughout the offset frequencies with the output jitter of only 6ps and dynamic current consumption of 2.767 mA.
Supervisors:
Ola Tylstedt, Catena Wireless Electronics AB
Henrik Sjöland, Lund Tekniska Högskola
Master Thesis 30 ECTS credits in Physics 2014
Department of Physics, Faculty of Science, Lund University (Less)
Please use this url to cite or link to this publication:
author
Gupta, Kamal LU
supervisor
organization
alternative title
Dual Loop Feedback DLL Based Frequency Multiplier
course
FYSM31 20141
year
type
H2 - Master's Degree (Two Years)
subject
keywords
reference multiplier, Frequency synthesizer, Frequency multiplier, PLL, DLL, Delay locked loop, VCDL, inverter-based VCDL, charge pump, XOR phase detector, phase noise, 4X multiplier
language
English
id
5277351
date added to LUP
2017-07-04 15:47:19
date last changed
2017-07-04 15:47:19
@misc{5277351,
  abstract     = {This master’s thesis project report deals with the design of multiplier for the reference signal to the Phase Locked Loop (PLL) used in WLAN application. The reference multiplier designed is based on a newly proposed architecture of dual loop feedback Delay Locked Loop (DLL) in which multiplication is performed within the loops. To lock the DLL, input signal is required to be delayed only for three by eighth of the period of input reference signal. The linear tuning range of the inverter-based voltage control delay line (VCDL) has been extended by making minimal modification in the circuit. Introduced VCDL shows good phase noise performance as less number of delay units are used due to wider delay range. The effect of reference multiplier’s jitter and spurs on the PLL’s performance has been analyzed. The circuit has been implemented in 55 nm CMOS technology from Global Foundry. For 160 MHz output signal, simulated results show an average of 4.5 dBc/Hz improvement in phase noise throughout the offset frequencies with the output jitter of 6 ps and dynamic current consumption of 2.767 mA},
  author       = {Gupta, Kamal},
  keyword      = {reference multiplier,Frequency synthesizer,Frequency multiplier,PLL,DLL,Delay locked loop,VCDL,inverter-based VCDL,charge pump,XOR phase detector,phase noise,4X multiplier},
  language     = {eng},
  note         = {Student Paper},
  title        = {DLL Based Reference Multiplier for the use in a PLL for WLAN applications},
  year         = {2015},
}