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High speed backbone for FPGA at ESS

Andersson, Max LU and Jönsson, Gabriel (2016) EITM01 20152
Department of Electrical and Information Technology
Abstract
The purpose of this project is to reverse engineer and re-design a PCI Express communication system which is currently being used at ESS in Lund. The current model is non-modifiable and our goal is to create a system open for customization. The aspects explored are communication between hardware and software using PCI Express, data handling and arbitration, direct memory access and how these can be implemented in hardware. We have successfully re-created the original design with a fully utilized read interface and a significantly slower write interface. The write function has been studied to find possible options to improve the current design. This system will be installed in 150 different parts of the accelerator and although it is a... (More)
The purpose of this project is to reverse engineer and re-design a PCI Express communication system which is currently being used at ESS in Lund. The current model is non-modifiable and our goal is to create a system open for customization. The aspects explored are communication between hardware and software using PCI Express, data handling and arbitration, direct memory access and how these can be implemented in hardware. We have successfully re-created the original design with a fully utilized read interface and a significantly slower write interface. The write function has been studied to find possible options to improve the current design. This system will be installed in 150 different parts of the accelerator and although it is a small part, it will be vital for the overall performance. (Less)
Popular Abstract
What we have done is to reverse engineer a PCI Express (PCIe) communication system between customized hardware and a Linux computer. The original hardware design is non-modifiable and our goal is to create a system open for customization. We have successfully re-created the original design and researched possible improvements. This system will be installed in 150 different parts of the European Spallation Source (ESS). Although it is a small part, it will be vital for the overall performance of the facility.
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author
Andersson, Max LU and Jönsson, Gabriel
supervisor
organization
alternative title
Digital communication system for a proton accelerator
course
EITM01 20152
year
type
H2 - Master's Degree (Two Years)
subject
keywords
Digital, FPGA, communication, hardware, software, PCIe, express, high, speed, linux, interface, memory, DMA, direct, access
report number
LU/LTH-EIT 2016-482
language
English
id
8564512
date added to LUP
2016-01-26 08:46:02
date last changed
2016-05-11 14:21:59
@misc{8564512,
  abstract     = {The purpose of this project is to reverse engineer and re-design a PCI Express communication system which is currently being used at ESS in Lund. The current model is non-modifiable and our goal is to create a system open for customization. The aspects explored are communication between hardware and software using PCI Express, data handling and arbitration, direct memory access and how these can be implemented in hardware. We have successfully re-created the original design with a fully utilized read interface and a significantly slower write interface. The write function has been studied to find possible options to improve the current design. This system will be installed in 150 different parts of the accelerator and although it is a small part, it will be vital for the overall performance.},
  author       = {Andersson, Max and Jönsson, Gabriel},
  keyword      = {Digital,FPGA,communication,hardware,software,PCIe,express,high,speed,linux,interface,memory,DMA,direct,access},
  language     = {eng},
  note         = {Student Paper},
  title        = {High speed backbone for FPGA at ESS},
  year         = {2016},
}