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Vertical heterostructure III-V nanowire MOSFETs

Jönsson, Adam LU (2016) In Vertical heterostructure III-V nanowire MOSFETs EITM01 20161
Department of Electrical and Information Technology
Abstract
If cars had developed as fast as processors they would go at 470,000 mph, get 100,000 miles to the gallon, and cost 3 cents" claims Paul Ottelini, Intel CEO 2005-2013. This serves as a reminder of how fast the field of nanoelectronics is developing due to constant demand for faster and more energy efficient integrated circuits. The still ongoing electronics revolution was accelerated by the innovation of one simple and elegant device, namely the Si-based metal-oxide-semiconductor-field-effect-transisor MOSFET in 1959. The pillar of economic growth has since been based on downscaling the MOSFET and increasing the density of transistor per chip area. Downscaling of the transistor has favourably led to more efficient and faster devices.... (More)
If cars had developed as fast as processors they would go at 470,000 mph, get 100,000 miles to the gallon, and cost 3 cents" claims Paul Ottelini, Intel CEO 2005-2013. This serves as a reminder of how fast the field of nanoelectronics is developing due to constant demand for faster and more energy efficient integrated circuits. The still ongoing electronics revolution was accelerated by the innovation of one simple and elegant device, namely the Si-based metal-oxide-semiconductor-field-effect-transisor MOSFET in 1959. The pillar of economic growth has since been based on downscaling the MOSFET and increasing the density of transistor per chip area. Downscaling of the transistor has favourably led to more efficient and faster devices. MOSFETs today are approaching sizes which only include few monolayers of atoms, basically dimensions of a few nanometer. Conventional electronics has thus been pushed into the quantum realm forcing future improvements to be based on innovation rather than simply downscaling. To win the battle against Heisenberg's uncertainty leading to leakage currents and various other effect due to reduced size, new 3d geometries has been introduced. Amongst these new geometries is the bottom up approach utilizing vertical nanowires. The vertical geometry also enables easier integration of alternative high mobility semiconductor materials on a Si substrate. A potential canditate for integration on Si is the III-V compound semiconductors due improvements in charge carrier transport capabilities.

To further motivate a switch in transistor geometry the full infrastructure of devices need to be present, not only satisfying the logical domain. Therefore, in parallel to the digital branch, a wish for developing better analog RF-transistors is present. The requirements for an RF-transistor are quite different where stability and high frequency signal gain is of importance. In an RF circuit power dissipation can be sacrificed for increased performance, lending more room for new innovations.

In this thesis the use of the vertical nanowire geometry for MOSFET is further investigated by implementing a III-V, InAs/InGaAs, graded heterostructure, inside the channel, optimized for increased stability and low resistance ohmic-contacts. A Si-substrate with grown III-V nanowires, on top of a InAs buffer layer, is provided and afterwards processed into a complete set of devices. The orientation of the grading is chosen with an abrupt junction from the InAs buffer layer to InGaAs slowly graded back to InAs at the top, by implementing 550 nm long nanowires. The measured DC-characteristics indicates a presence of the heterostructure due to good saturation, low output conductance g_d = 2 uS/um at V_ds = 0.5 V and V_gs = 0.5 V. Amplification and current does not reach intended values because of large access resistance, R_c = 1500 Ohm*um, with transconductance g_m,max = 280 uS/um. Good gate control is indicated with devices showcasing low sub-threshold swing SS down to 80 mV/dec.

Motivation of introducing a heterostructure is clear due to higher breakdown and increased linearity but the choice of the grading orientation is not. Contact resistance is mostly originating from the source side, which means that there is large room for improvement by tweaking the process. The nanowires also had a tendency to collapse which decreased the performance. In other words the theory of implementing a heterostructure with abrupt junction for larger breakdown voltage and increased linearity is promising and cannot yet be disregarded. (Less)
Popular Abstract (Swedish)
Om bilar hade utvecklats så snabbt som processorer skulle de färdas i en hastighet på 760,000 km/h, gå 42 000 km per liter och kosta 25 öre" hävdar Paul Ottelini, Intel VD mellan 2005-2013. Detta påminner oss om vilken rasande fart utvecklingen har inom nanoelektronik branschen där elektroniska kretsar ständigt blivit billigare samt mindre under det senaste halvseklet. Miniatyriseringen har fördelaktigt gått hand i hand med ökad prestanda. Den huvudsakliga beståndsdelen som används i dessa kretsar, som exempelvis en processor, är en transistor. Uppgiften för en transistor är att styra strömmar på så sätt att de kan stängas av eller på.

Transistorn består av tre huvudsakliga elektroder, där elektrisk spänning kan appliceras. Mellan två... (More)
Om bilar hade utvecklats så snabbt som processorer skulle de färdas i en hastighet på 760,000 km/h, gå 42 000 km per liter och kosta 25 öre" hävdar Paul Ottelini, Intel VD mellan 2005-2013. Detta påminner oss om vilken rasande fart utvecklingen har inom nanoelektronik branschen där elektroniska kretsar ständigt blivit billigare samt mindre under det senaste halvseklet. Miniatyriseringen har fördelaktigt gått hand i hand med ökad prestanda. Den huvudsakliga beståndsdelen som används i dessa kretsar, som exempelvis en processor, är en transistor. Uppgiften för en transistor är att styra strömmar på så sätt att de kan stängas av eller på.

Transistorn består av tre huvudsakliga elektroder, där elektrisk spänning kan appliceras. Mellan två av elektroderna kan en ström färdas såsom igenom ett vanligt motstånd. Med den tredje, som brukar kallas gate, kan resistansen manipuleras vilket ändrar strömmen som färdas mellan de två övriga elektroderna. I en dator krävs det att transistorn ska fungera som ett relä, helt enkelt en effektiv av/på knapp. Här är prestandan väldigt beroende av hur många transistorer, logiska kretsar, som får plats på ett chip för att i slutändan kunna utföra många beräkningar samtidigt.

För analoga applikationer däremot, i till exempel radiosändare och mottagare, ställs andra krav. Här kan det räcka med endast ett fåtal transistorer som effektivt kan tolka och förstärka en signal som varierar över tiden. När frekvensen på signalen som ska sändas, eller mottagas, ökar kan även mer information transporteras. I framtiden krävs därmed pålitliga transistorer som hinner tolka snabba strömändringar på grund av signal-frekvenser på flera 100 GHz.

I den digitala världen har den pågående miniatyriseringen av de logiska kretsarna lett till att många dimensioner endast är tiotals atomer. Därmed uppkommer flera utmaningar vid vidare miniatyrisering av kretsarna som leder till att man fullkomligt förlorar kontrollen över gaten. För fortsatt utveckling tittar man då på alternativa material samt andra utformningar av transistorerna. Det tål att nämnas att det som sker i den digitala världen självklart påverkar den analoga sfären.

I detta arbete har möjligheten att skapa transistorer av stående cylindriska pelare, även kallade nanotrådar, undersökts. På dessa nanotrådar kan gaten lindas runt själva tråden för att få bästa möjliga kontroll av strömmen. Dessutom är olika material blandade inuti tråden för att uppnå gynnsamma villkor. Dessa villkor är att elektroner enkelt ska kunna färdas genom materialet samtidigt som transistorn ska vara pålitlig vid ett stort omfång av applicerad spänning på elektroderna. Därför har en blandning av indiumarsenid, som bidrar med hög rörlighet för elektroner, och indiumgalliumarsenid använts. Det sistnämnda materialet bidrar med extra pålitlighet. Den färdiga transistorn uppvisade god kontroll av strömmen med aningen begränsad prestanda. Notera att dessa transistorer är, i grund och botten, skapade ovanpå ett kiselprov, vilket gör denna teknologi överförbar till industriell skala. (Less)
Please use this url to cite or link to this publication:
author
Jönsson, Adam LU
supervisor
organization
course
EITM01 20161
year
type
H2 - Master's Degree (Two Years)
subject
keywords
MOSFET, transistor, heterostructure, III-V, RF, semiconductor, silicon, fabrication, electronics
publication/series
Vertical heterostructure III-V nanowire MOSFETs
report number
LU/LHT-EIT 2016-537
language
English
id
8889989
date added to LUP
2016-08-31 09:11:53
date last changed
2016-09-07 08:17:54
@misc{8889989,
  abstract     = {If cars had developed as fast as processors they would go at 470,000 mph, get 100,000 miles to the gallon, and cost 3 cents" claims Paul Ottelini, Intel CEO 2005-2013. This serves as a reminder of how fast the field of nanoelectronics is developing due to constant demand for faster and more energy efficient integrated circuits. The still ongoing electronics revolution was accelerated by the innovation of one simple and elegant device, namely the Si-based metal-oxide-semiconductor-field-effect-transisor MOSFET in 1959. The pillar of economic growth has since been based on downscaling the MOSFET and increasing the density of transistor per chip area. Downscaling of the transistor has favourably led to more efficient and faster devices. MOSFETs today are approaching sizes which only include few monolayers of atoms, basically dimensions of a few nanometer. Conventional electronics has thus been pushed into the quantum realm forcing future improvements to be based on innovation rather than simply downscaling. To win the battle against Heisenberg's uncertainty leading to leakage currents and various other effect due to reduced size, new 3d geometries has been introduced. Amongst these new geometries is the bottom up approach utilizing vertical nanowires. The vertical geometry also enables easier integration of alternative high mobility semiconductor materials on a Si substrate. A potential canditate for integration on Si is the III-V compound semiconductors due improvements in charge carrier transport capabilities. 

To further motivate a switch in transistor geometry the full infrastructure of devices need to be present, not only satisfying the logical domain. Therefore, in parallel to the digital branch, a wish for developing better analog RF-transistors is present. The requirements for an RF-transistor are quite different where stability and high frequency signal gain is of importance. In an RF circuit power dissipation can be sacrificed for increased performance, lending more room for new innovations.

In this thesis the use of the vertical nanowire geometry for MOSFET is further investigated by implementing a III-V, InAs/InGaAs, graded heterostructure, inside the channel, optimized for increased stability and low resistance ohmic-contacts. A Si-substrate with grown III-V nanowires, on top of a InAs buffer layer, is provided and afterwards processed into a complete set of devices. The orientation of the grading is chosen with an abrupt junction from the InAs buffer layer to InGaAs slowly graded back to InAs at the top, by implementing 550 nm long nanowires. The measured DC-characteristics indicates a presence of the heterostructure due to good saturation, low output conductance g_d = 2 uS/um at V_ds = 0.5 V and V_gs = 0.5 V. Amplification and current does not reach intended values because of large access resistance, R_c = 1500 Ohm*um, with transconductance g_m,max = 280 uS/um. Good gate control is indicated with devices showcasing low sub-threshold swing SS down to 80 mV/dec. 

Motivation of introducing a heterostructure is clear due to higher breakdown and increased linearity but the choice of the grading orientation is not. Contact resistance is mostly originating from the source side, which means that there is large room for improvement by tweaking the process. The nanowires also had a tendency to collapse which decreased the performance. In other words the theory of implementing a heterostructure with abrupt junction for larger breakdown voltage and increased linearity is promising and cannot yet be disregarded.},
  author       = {Jönsson, Adam},
  keyword      = {MOSFET,transistor,heterostructure,III-V,RF,semiconductor,silicon,fabrication,electronics},
  language     = {eng},
  note         = {Student Paper},
  series       = {Vertical heterostructure III-V nanowire MOSFETs},
  title        = {Vertical heterostructure III-V nanowire MOSFETs},
  year         = {2016},
}