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Integration of a Digital Built-in Self-Test for On-Chip Memories

Luo, Xiao LU and Nouripayam, Masoud LU (2017) EITM02 20171
Department of Electrical and Information Technology
Abstract
The ability of testing on-chip circuitry is extremely essential to ASIC implemen- tations today. However, providing functional tests and verification for on-chip (embedded) memories always poses a huge number of challenges to the designer.

Therefore, a co-existing automated built-in self-test block with the Design Under Test (DUT) seems crucial to provide comprehensive, efficient and robust testing features. The target DUT of this thesis project is the state-of-the-arts Ultra Low Power (ULP) dual-port SRAMs designed in ASIC group of EIT department at Lund University.
This thesis starts from system RTL modeling and verification from an earlier project, and then goes through ASIC design phase in 28 nm FD-SOI technology from... (More)
The ability of testing on-chip circuitry is extremely essential to ASIC implemen- tations today. However, providing functional tests and verification for on-chip (embedded) memories always poses a huge number of challenges to the designer.

Therefore, a co-existing automated built-in self-test block with the Design Under Test (DUT) seems crucial to provide comprehensive, efficient and robust testing features. The target DUT of this thesis project is the state-of-the-arts Ultra Low Power (ULP) dual-port SRAMs designed in ASIC group of EIT department at Lund University.
This thesis starts from system RTL modeling and verification from an earlier project, and then goes through ASIC design phase in 28 nm FD-SOI technology from ST-Microelectronics. All scripts during the ASIC design phase are developed in TCL.

This design is implemented with multiple power domains (using CPF approach and introducing level-shifters at crossing-points between domains) and multiple clock sources in order to make it possible to perform various measurements with a high reliability on different flavours of a dual-port SRAM. (Less)
Popular Abstract
This design is able to reduce dramatically the complexity of verification and measurement to integrated memories.


This digital integrated circuit (IC) is developed as an application-specific IC (ASIC) chip for functional verification of integrated memories and measuring them in different aspects such as power consumption.

The design is automated and capable of being reconfigured easily in terms of required actions and data for testing on-chip memories. Put it in other words, this design has automated and optimized the generation of what data to be stored on which location on memories as well as how they have been treated and interpreted later on. For instance, it refreshes and delivers different operation modes and working... (More)
This design is able to reduce dramatically the complexity of verification and measurement to integrated memories.


This digital integrated circuit (IC) is developed as an application-specific IC (ASIC) chip for functional verification of integrated memories and measuring them in different aspects such as power consumption.

The design is automated and capable of being reconfigured easily in terms of required actions and data for testing on-chip memories. Put it in other words, this design has automated and optimized the generation of what data to be stored on which location on memories as well as how they have been treated and interpreted later on. For instance, it refreshes and delivers different operation modes and working patterns to the entire test system in order to fully utilize integrated memories, of which such an automation is instructed by the stimuli to the chip. Besides, the pattern generation of the stimuli is implemented on MATLAB in an automated way.

Due to constant advancements in chip manufacturing technology, more devices are squeezed into the same silicon area. Meaning that in order to monitor more internal signals introduced by the increased complexity of the circuits, more dedicated input/output ports (the physical interface between the chip internal signals and outside world) are required, that makes the chip bonding and testing in the future difficult and time-consuming. Additionally, memories usually have a bigger number of pins for signal reactions than other circuit blocks do, the method of dealing with so many pins should also be taken into account.

Thus, a few techniques are adopted in this system to assist the designers deal with all mentioned issues.

Once the ASIC chip has been fabricated (manufactured) and bonded, the on-chip memories can be tested directly on a printed circuit board in a simple and flexible way: Once test instruction input is loaded into the chip, the system starts to update the system settings and then to generate the internal configurations(parameters) so that all different operations, modes or instructions related to memory testing are automatically processed. (Less)
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author
Luo, Xiao LU and Nouripayam, Masoud LU
supervisor
organization
course
EITM02 20171
year
type
H2 - Master's Degree (Two Years)
subject
keywords
BIST SRAM verification test self-test dual-port ASIC
report number
LU/LTH-EIT 2017-612
language
English
id
8928977
date added to LUP
2017-12-12 15:32:27
date last changed
2017-12-12 15:32:27
@misc{8928977,
  abstract     = {The ability of testing on-chip circuitry is extremely essential to ASIC implemen- tations today. However, providing functional tests and verification for on-chip (embedded) memories always poses a huge number of challenges to the designer.

Therefore, a co-existing automated built-in self-test block with the Design Under Test (DUT) seems crucial to provide comprehensive, efficient and robust testing features. The target DUT of this thesis project is the state-of-the-arts Ultra Low Power (ULP) dual-port SRAMs designed in ASIC group of EIT department at Lund University.
This thesis starts from system RTL modeling and verification from an earlier project, and then goes through ASIC design phase in 28 nm FD-SOI technology from ST-Microelectronics. All scripts during the ASIC design phase are developed in TCL.

This design is implemented with multiple power domains (using CPF approach and introducing level-shifters at crossing-points between domains) and multiple clock sources in order to make it possible to perform various measurements with a high reliability on different flavours of a dual-port SRAM.},
  author       = {Luo, Xiao and Nouripayam, Masoud},
  keyword      = {BIST SRAM verification test self-test dual-port ASIC},
  language     = {eng},
  note         = {Student Paper},
  title        = {Integration of a Digital Built-in Self-Test for On-Chip Memories},
  year         = {2017},
}