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Hardware-software model co-simulation for GPU IP development

Gancedo Rodrigo, Jaime LU (2018) EITM02 20172
Department of Electrical and Information Technology
Abstract
This Master's thesis project aims to explore the possibility of a mixed simulation
environment in which parts of a software model for emulating a hardware design
may be swapped with their corresponding RTL description. More specifically, this
work focuses on the sofware model for Arm's next-generation Mali GPU, which
is used to understand system on chip properties, including functionality and performance. A component of this model (written in C++) is substituted with its
hardware model (written in SystemVerilog) to be able to run simulations in a system
context at a faster emulation speed, and with higher accuracy in the results
compared to a pure-software model execution. For this, a "co-simulation" environment is developed, using... (More)
This Master's thesis project aims to explore the possibility of a mixed simulation
environment in which parts of a software model for emulating a hardware design
may be swapped with their corresponding RTL description. More specifically, this
work focuses on the sofware model for Arm's next-generation Mali GPU, which
is used to understand system on chip properties, including functionality and performance. A component of this model (written in C++) is substituted with its
hardware model (written in SystemVerilog) to be able to run simulations in a system
context at a faster emulation speed, and with higher accuracy in the results
compared to a pure-software model execution. For this, a "co-simulation" environment is developed, using SystemVerilog's DPI-C as the main communication
interface between C++ and SystemVerilog. The proposed environment contains
new software and hardware blocks to enable the desired objective without major
modifications in neither the software Mali model nor the substituted component.
Metrics and results for characterizing this co-simulation environment are also provided, namely timing accuracy, data correctness and simulation time with respect
to other previously available simulation options. These results hope to show that
the proposed environment may open new use-cases and improve development and
verification time of hardware components in a system such as the Mali GPU. (Less)
Popular Abstract
The possibility of combining hardware designs and software in the same simulation environment opens new options and improves significantly the flexibility of verification processes as well as characterization time of electronic designs. A practical method to realize this is developed and presented in this work for the case of a real Graphics Processing Unit IP.

Nowadays electronics designers and manufacturers compete in an increasingly faster race to be able to provide the best and most efficient solutions to the market's expectations. The easiest example is the tendency of smartphone designers to provide a brand-new mobile phone model every year to meet consumers' demand. To meet these tighter and tighter deadlines, these companies... (More)
The possibility of combining hardware designs and software in the same simulation environment opens new options and improves significantly the flexibility of verification processes as well as characterization time of electronic designs. A practical method to realize this is developed and presented in this work for the case of a real Graphics Processing Unit IP.

Nowadays electronics designers and manufacturers compete in an increasingly faster race to be able to provide the best and most efficient solutions to the market's expectations. The easiest example is the tendency of smartphone designers to provide a brand-new mobile phone model every year to meet consumers' demand. To meet these tighter and tighter deadlines, these companies need to find new ways of designing and verifying their products faster and more efficiently. In this context enters the work presented in this thesis: One of many possible solutions to improve the verification time of a hardware unit/block.

Digital electronic circuits are commonly designed and modelled using Hardware Design Languages (HDLs), which are similar to computer languages such as C or Java, but different in the sense that HDLs actually describe the physical layout and connections of a digital circuit. These HDL designs can be simulated to verify their correct performance and characteristics with very high detail but, at the same time, this type of simulations are costly in terms of computational time and resources, due to the nature of the magnitudes and mechanisms being replicated on the computer running the simulation.

On the other hand, software is written in computer languages directly, compiled to machine language and run sequentially by computers, in a much faster and efficient manner. Therefore, what if the best of the two could be combined to simulate a digital design in which only a specific internal block is described in a HDL while the rest of the design is a software program? This would allow to reduce the simulation time of that block greatly, while at the same type preserve the accuracy that a simulation of a HDL design can provide.

This thesis work is based on a specific part of Arm's next-generation Mali Graphics Processing Unit (GPU), for which a solution for mixing hardware and software in the same simulation is proposed. For this specific case, such mechanism will allow to improve the development and testing time of new features for a Mali hardware IP, while at the same time open new use-cases for future work in this direction. (Less)
Please use this url to cite or link to this publication:
author
Gancedo Rodrigo, Jaime LU
supervisor
organization
course
EITM02 20172
year
type
H2 - Master's Degree (Two Years)
subject
report number
LU/LTH-EIT 2018-626
language
English
id
8938914
date added to LUP
2018-04-20 16:48:16
date last changed
2018-04-20 16:48:16
@misc{8938914,
  abstract     = {{This Master's thesis project aims to explore the possibility of a mixed simulation
environment in which parts of a software model for emulating a hardware design
may be swapped with their corresponding RTL description. More specifically, this
work focuses on the sofware model for Arm's next-generation Mali GPU, which
is used to understand system on chip properties, including functionality and performance. A component of this model (written in C++) is substituted with its
hardware model (written in SystemVerilog) to be able to run simulations in a system
context at a faster emulation speed, and with higher accuracy in the results
compared to a pure-software model execution. For this, a "co-simulation" environment is developed, using SystemVerilog's DPI-C as the main communication
interface between C++ and SystemVerilog. The proposed environment contains
new software and hardware blocks to enable the desired objective without major
modifications in neither the software Mali model nor the substituted component.
Metrics and results for characterizing this co-simulation environment are also provided, namely timing accuracy, data correctness and simulation time with respect
to other previously available simulation options. These results hope to show that
the proposed environment may open new use-cases and improve development and
verification time of hardware components in a system such as the Mali GPU.}},
  author       = {{Gancedo Rodrigo, Jaime}},
  language     = {{eng}},
  note         = {{Student Paper}},
  title        = {{Hardware-software model co-simulation for GPU IP development}},
  year         = {{2018}},
}