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- 2022
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Mark
FPGA Implementation of Feature Matching in ORB-SLAM2
- Master (Two yrs)
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Mark
Efficient High-level Synthesis Implementation of massive MIMO Processing on RFSoC
- Master (Two yrs)
-
Mark
Investigating Machine Learning for verification of AMBA APB protocol.
- Master (Two yrs)
- 2021
-
Mark
Design parameterizable filter using High Level Synthesis
- Master (Two yrs)
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Mark
Customization of Ibex RISC-V Processor Core
(2021) In Customization of Ibex RISC-V Processor Core EITM02 20211
Department of Electrical and Information Technology- Master (Two yrs)
- 2020
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Mark
High-Level Synthesis for Efficient Design and Verification
- Master (Two yrs)
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Mark
Implementation of a Deep Learning Inference Accelerator on the FPGA.
- Master (Two yrs)
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Mark
Low Power Pre-Distorter Design For 5G Radio Using Machine Learning
- Master (Two yrs)
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Mark
Self-organizing Maps for Digital Pre-distortion
- Master (Two yrs)
- 2019
-
Mark
Implementation of an 8-bit Dynamic Fixed-Point Convolutional Neural Network for Human Sign Language Recognition on a Xilinx FPGA Board
- Master (Two yrs)