Converging SPI_S Designs: An Evaluation of Configurable IP Development
(2025) EITM01 20251Department of Electrical and Information Technology
- Abstract
- This thesis explores the configurability of IPs for ASICs by looking into the design of SPI_S, an IP used for communication between ASICs and peripheral devices. Configurability is explored to reduce manual labor when requirements set on the IP change between projects. The thesis looks into the challenges of developing a configurable IP, including architecture, design, and verification. In addition, how configurability affects performance, area, and power consumption. The results show that SPI_S can be made more configurable and still meet requirements set on performance. However, area and power consumption tend to increase, though tying configuration ports to fixed values enables synthesis optimizations that can significantly reduce this... (More)
- This thesis explores the configurability of IPs for ASICs by looking into the design of SPI_S, an IP used for communication between ASICs and peripheral devices. Configurability is explored to reduce manual labor when requirements set on the IP change between projects. The thesis looks into the challenges of developing a configurable IP, including architecture, design, and verification. In addition, how configurability affects performance, area, and power consumption. The results show that SPI_S can be made more configurable and still meet requirements set on performance. However, area and power consumption tend to increase, though tying configuration ports to fixed values enables synthesis optimizations that can significantly reduce this overhead when static configurations are used. Configurability also comes with challenges throughout the development cycle. During development, a comprehensive UVM testbench developed alongside the design is of utmost importance, to ensure that implemented features are properly validated in all the different configurations. (Less)
- Popular Abstract
- Today's electronic devices, like smartphones and computers, rely on tiny, complex chips that handle specific tasks. These chips, also called ASICs (Application Specific Integrated Circuit), are brought together by using special hardware building blocks called IPs (Intellectual Property) blocks. Common within IP blocks are modules that handle communication with other devices, such as memory or sensors, and that is achieved by using standardized communication protocols. A common communication protocol for this task is SPI (Serial Peripheral Interface).
In this thesis, we explore how to make a communication IP called SPI\_S more configurable, meaning, that instead of creating a new version every time requirements change between products,... (More) - Today's electronic devices, like smartphones and computers, rely on tiny, complex chips that handle specific tasks. These chips, also called ASICs (Application Specific Integrated Circuit), are brought together by using special hardware building blocks called IPs (Intellectual Property) blocks. Common within IP blocks are modules that handle communication with other devices, such as memory or sensors, and that is achieved by using standardized communication protocols. A common communication protocol for this task is SPI (Serial Peripheral Interface).
In this thesis, we explore how to make a communication IP called SPI\_S more configurable, meaning, that instead of creating a new version every time requirements change between products, we design one flexible version that can adapt by simply adjusting its settings. This hopefully reduces manual work and speeds up the development of new products.
However, making a flexible design comes with challenges. Aside from being a more complicated design, it is also more complex to test because you have to make sure all possible configurations work correctly. That is why we also developed a testing system using a method called UVM, which helps automatically check if the design behaves as it should.
Our results show that configurability is definitely possible and can meet performance needs, but it leads to higher power use and takes up more space on the chip. Overall, this work highlights the design and verification process, challenges when developing configurable IP, and the importance of having a strong testing approach when working with complex hardware designs. (Less)
Please use this url to cite or link to this publication:
http://lup.lub.lu.se/student-papers/record/9202990
- author
- Lundgren, Sakarias LU and Modica, Benjamin LU
- supervisor
- organization
- course
- EITM01 20251
- year
- 2025
- type
- H2 - Master's Degree (Two Years)
- subject
- keywords
- Configurable IP, IP development
- report number
- LU/LTH-EIT 2025-1081
- language
- English
- id
- 9202990
- date added to LUP
- 2025-06-24 12:16:58
- date last changed
- 2025-06-24 12:16:58
@misc{9202990,
abstract = {{This thesis explores the configurability of IPs for ASICs by looking into the design of SPI_S, an IP used for communication between ASICs and peripheral devices. Configurability is explored to reduce manual labor when requirements set on the IP change between projects. The thesis looks into the challenges of developing a configurable IP, including architecture, design, and verification. In addition, how configurability affects performance, area, and power consumption. The results show that SPI_S can be made more configurable and still meet requirements set on performance. However, area and power consumption tend to increase, though tying configuration ports to fixed values enables synthesis optimizations that can significantly reduce this overhead when static configurations are used. Configurability also comes with challenges throughout the development cycle. During development, a comprehensive UVM testbench developed alongside the design is of utmost importance, to ensure that implemented features are properly validated in all the different configurations.}},
author = {{Lundgren, Sakarias and Modica, Benjamin}},
language = {{eng}},
note = {{Student Paper}},
title = {{Converging SPI_S Designs: An Evaluation of Configurable IP Development}},
year = {{2025}},
}