Portable Stimulus for ASIC Verification
(2025) EITM02 20251Department of Electrical and Information Technology
- Abstract
- In modern ASIC verification, bridging the gap between IP-level and system-level test environments is a major challenge, especially as system-on-chip (SoC) complexity grows. This thesis presents a novel methodology leveraging the Accellera Portable Stimulus Standard to enable portable, reusable verification scenarios across these levels. The approach introduces a pre-runtime signal forcing mechanism (backdoor forcing technique) that allows certain internal register states to be preset via backdoor access before simulation begins. This ensures that complex scenarios and corner cases can be exercised from the very start of test execution, ultimately improving coverage and efficiency.
Using the Cadence Perspec System Verifier tool as the... (More) - In modern ASIC verification, bridging the gap between IP-level and system-level test environments is a major challenge, especially as system-on-chip (SoC) complexity grows. This thesis presents a novel methodology leveraging the Accellera Portable Stimulus Standard to enable portable, reusable verification scenarios across these levels. The approach introduces a pre-runtime signal forcing mechanism (backdoor forcing technique) that allows certain internal register states to be preset via backdoor access before simulation begins. This ensures that complex scenarios and corner cases can be exercised from the very start of test execution, ultimately improving coverage and efficiency.
Using the Cadence Perspec System Verifier tool as the Portable Stimulus Standard development and execution platform, a unified model was developed to generate tests for both Universal Verification Methodology simulations and software-driven verification. From a single abstract model description in the standard, the methodology automatically produces testbench sequences for IP-level verification and corresponding C test code to run on an embedded processor at the top level. This dual-output approach supports seamless test reuse: the same test intent is executed in both a low-level simulation environment and a high-level software context, ensuring consistent verification across the ASIC hierarchy. The approach also integrates IP-XACT (IEEE 1685), an IP metadata standard, to automate creation of the PSS register model. By extracting register definitions and register-transfer-level paths from IP-XACT, the flow auto-generates backdoor register access functions aligned with the design’s specification, eliminating the need for the previously used methodology and minimizing manual effort in register modeling, reducing errors.
The results demonstrate several key benefits to verification. The portable stimulus approach provided consistent testing at both IP and full-chip levels without duplicating effort across environments. Teams working on IP-level and system-level verification can now collaborate more effectively via a shared PSS model, which improves communication and eliminates ambiguities in test intent. The backdoor forcing capability also synchronizes initial conditions between tests, ensuring that hardware state and test assumptions match—this accelerates debug and guarantees correct stimulus setup.
The generated tests were integrated into existing testbenches with minimal modifications, highlighting the methodology’s compatibility with standard verification flows. Overall, the PSS-driven approach streamlines the verification process and improves efficiency by enabling high reuse, and more effective teamwork. It showcases how PSS, supported by commercial tools like Cadence Perspec, can serve as a unifying layer across verification domains, ultimately leading to a more scalable and sustainable ASIC verification flow. (Less)
Please use this url to cite or link to this publication:
http://lup.lub.lu.se/student-papers/record/9205661
- author
- Aslanidis, Antonios LU
- supervisor
-
- Liang Liu LU
- organization
- course
- EITM02 20251
- year
- 2025
- type
- H2 - Master's Degree (Two Years)
- subject
- keywords
- PSS, UVM, ASIC
- report number
- LU/LTH-EIT 2025-1076
- language
- English
- id
- 9205661
- date added to LUP
- 2025-06-26 13:16:59
- date last changed
- 2025-06-26 13:16:59
@misc{9205661,
abstract = {{In modern ASIC verification, bridging the gap between IP-level and system-level test environments is a major challenge, especially as system-on-chip (SoC) complexity grows. This thesis presents a novel methodology leveraging the Accellera Portable Stimulus Standard to enable portable, reusable verification scenarios across these levels. The approach introduces a pre-runtime signal forcing mechanism (backdoor forcing technique) that allows certain internal register states to be preset via backdoor access before simulation begins. This ensures that complex scenarios and corner cases can be exercised from the very start of test execution, ultimately improving coverage and efficiency.
Using the Cadence Perspec System Verifier tool as the Portable Stimulus Standard development and execution platform, a unified model was developed to generate tests for both Universal Verification Methodology simulations and software-driven verification. From a single abstract model description in the standard, the methodology automatically produces testbench sequences for IP-level verification and corresponding C test code to run on an embedded processor at the top level. This dual-output approach supports seamless test reuse: the same test intent is executed in both a low-level simulation environment and a high-level software context, ensuring consistent verification across the ASIC hierarchy. The approach also integrates IP-XACT (IEEE 1685), an IP metadata standard, to automate creation of the PSS register model. By extracting register definitions and register-transfer-level paths from IP-XACT, the flow auto-generates backdoor register access functions aligned with the design’s specification, eliminating the need for the previously used methodology and minimizing manual effort in register modeling, reducing errors.
The results demonstrate several key benefits to verification. The portable stimulus approach provided consistent testing at both IP and full-chip levels without duplicating effort across environments. Teams working on IP-level and system-level verification can now collaborate more effectively via a shared PSS model, which improves communication and eliminates ambiguities in test intent. The backdoor forcing capability also synchronizes initial conditions between tests, ensuring that hardware state and test assumptions match—this accelerates debug and guarantees correct stimulus setup.
The generated tests were integrated into existing testbenches with minimal modifications, highlighting the methodology’s compatibility with standard verification flows. Overall, the PSS-driven approach streamlines the verification process and improves efficiency by enabling high reuse, and more effective teamwork. It showcases how PSS, supported by commercial tools like Cadence Perspec, can serve as a unifying layer across verification domains, ultimately leading to a more scalable and sustainable ASIC verification flow.}},
author = {{Aslanidis, Antonios}},
language = {{eng}},
note = {{Student Paper}},
title = {{Portable Stimulus for ASIC Verification}},
year = {{2025}},
}