Design Space Exploration and PPA Evaluation of ARM NI-700 Interconnect as a Replacement for NIC-400 in ASIC Architectures

Abstract

With the rapid evolution of semiconductor technology and the growing demand for high-performance, low-power System-on-Chip solutions, the design of efficient and scalable on-chip interconnect architectures has become a critical challenge in modern ASIC development. This thesis focuses on design space exploration of replacing multiple ARM CoreLink NIC-400 crossbar-based interconnects with a unified ARM CoreLink NI-700 Network-on-Chip interconnect within the same ASIC architecture, in order to improve scalability, performance, and power efficiency. The work addresses the increasing complexity of modern semiconductor products, where communication plays a significant role in meeting stringent Power, Performance, and Area targets.

Firstly, the study establishes a technical foundation by reviewing AMBA communication protocols (AXI, APB) and ARM CoreLink interconnect architectures, highlighting the design characteristics and limitations of NIC-400's crossbar-based approach compared to NI-700's NoC design. In addition, it introduces a general data collection methodology, especially the procedures used for power estimation.

Secondly, the research migrates an existing NIC-400-based interconnect to an NI-700 architecture through topology configuration and interface mapping. Four controlled experiments evaluate five NI-700 configurations, focusing on the impact of parameters such as wire mode, boundaries size, components placement, and GT element size.

Furthermore, experimental results indicate that high-performance NI-700 configurations achieve efficient power usage and acceptable area overhead compared to NIC-400 with physical design limit. NI-700's topology design flexibility allows physical design optimizations based on needs. While minimized configuration maintains acceptable sacrifice in performance with superior power and area efficiency, making it suitable for resource-limited ASICs.

Last but not least, the study concludes with viable guidelines for selecting between NIC-400 and NI-700 based on application, and outlines future work involving optimized topology generation, low-power and IDM feature integration, and multi-voltage domain support.

Popular Abstract

An Application Specific Integrated Circuit could be compared to a city, make it easier to understand the construction: processing units are the buildings, while interconnect is the city's transportation system. If the roads are poorly designed, the city will suffer from traffic jam. Similarly, the interconnect determines how efficiently processing units communicate. Even the most powerful processors can be held back once their internal communications have low efficiency.

In daily life, chips are everywhere, and their overall performance largely depend on efficient interconnection. For example, autonomous vehicles require on-board chips to process data instantly from cameras, radar, and navigation. Inefficient interconnect may introduce delays even safe risk. The fast and efficient communication between multiple components plays a significant role.

There are multiple ways to construct such a "transportation system" on a chip. Here, we focus on two main approaches: Crossbar and Network-on-Chip. Crossbar allows processing units to communicate with others directly, like giving every building its own private road to others. This method is suitable for a small design, but doesn't perform well with the growing of scalability and complexity of a chip. In contrast, Network-on-Chip acts as a communication network, like a city road network composed of highways and branch roads, while data travels through multiple routers instead of direct connections between each units. It provides higher scalability and flexibility for large-scale design.

Three key factors are used to evaluate interconnects, often called PPA: Power, Performance, and Area. Power refers to the energy consumed. Performance measures how well the interconnect handles traffic, which can be accessed by two metrics, latency and bandwidth: latency is like the travel time for one car to reach its destination, while bandwidth is like the number of lanes on the highway that decide how many cars can move at once. Area is like a physical space the roads occupy, building too many wide highways leaves little room for buildings. A good design must balance all three: reduce power, meet latency and bandwidth targets, and minimize area overhead.

This thesis replaces an on-chip interconnect design from a crossbar based ARM CoreLink NIC-400 to a NoC-based NI-700. It then compares these two interconnects on PPA. Each design parameter is changed once at a time to observe its exact effect. The work gives clear guidelines on when to pick NIC-400 or NI-700 based on needs. These findings help future SoC designers make informed interconnect choices and speed up the integration of more flexible NoC architectures.

• author: Li, Hao and Zhang, Qinzhen
• supervisor: Liang Liu; Moazzam Niazi
• organization: Department of Electrical and Information Technology
• course: EITM02 20251
• year: 2025
• type: H2 - Master's Degree (Two Years)
• subject: Technology and Engineering
• report number: LU/LTH-EIT 2025-1098
• language: English
• id: 9213673
• date added to LUP: 2025-10-09 12:53:56
• date last changed: 2025-10-09 12:53:56