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- 2024
-
Mark
Fast Prototyping of Massive MIMO User Equipment Using PYNQ
(
- Master (Two yrs)
- 2023
-
Mark
Beam-steered Modulation in Advanced Antenna System
(
- Master (Two yrs)
-
Mark
Exploring Ethernet Switching Architectures for Area-Efficient Low-End Switches
(
- Master (Two yrs)
-
Mark
Using Approximate Computing Circuits to Optimize Power of an ASIC
(
- Master (Two yrs)
-
Mark
High Level Synthesis for ASIC and FPGA
(
- Master (Two yrs)
-
Mark
Novel Method of ASIC interface IP development using HLS
(
- Master (Two yrs)
-
Mark
Hardware Accelerator of Bundle Adjustment Algorithm
(
- Master (Two yrs)
- 2022
-
Mark
FPGA Implementation of Feature Matching in ORB-SLAM2
(
- Master (Two yrs)
-
Mark
Efficient High-level Synthesis Implementation of massive MIMO Processing on RFSoC
(
- Master (Two yrs)
-
Mark
Investigating Machine Learning for verification of AMBA APB protocol.
(
- Master (Two yrs)
- 2021
-
Mark
Customization of Ibex RISC-V Processor Core
2021) In Customization of Ibex RISC-V Processor Core EITM02 20211(
Department of Electrical and Information Technology- Master (Two yrs)
-
Mark
Design parameterizable filter using High Level Synthesis
(
- Master (Two yrs)
- 2020
-
Mark
Implementation of a Deep Learning Inference Accelerator on the FPGA.
(
- Master (Two yrs)
-
Mark
Low Power Pre-Distorter Design For 5G Radio Using Machine Learning
(
- Master (Two yrs)
-
Mark
Self-organizing Maps for Digital Pre-distortion
(
- Master (Two yrs)
-
Mark
High-Level Synthesis for Efficient Design and Verification
(
- Master (Two yrs)
- 2019
-
Mark
Case study on Universal Verification Methodology(UVM) SystemC testbench for RTL verification
(
- Master (Two yrs)
-
Mark
Implementation of an 8-bit Dynamic Fixed-Point Convolutional Neural Network for Human Sign Language Recognition on a Xilinx FPGA Board
(
- Master (Two yrs)
-
Mark
Reduction of Crosstalk Distortion in 5G
(
- Master (Two yrs)
-
Mark
Arbitrary Decimation for High Sample Rates, Algorithm Design and FPGA implementation
(
- Master (Two yrs)
-
Mark
Performance Evaluation of MathWorks HDL Coder as a Vendor Independent DFE Generation
(
- Master (Two yrs)
-
Mark
Investigate Redundancy In Sounding Reference Signal Based Channel Estimates
(
- Master (Two yrs)
- 2018
-
Mark
Efficient DPD Coefficient Extraction For Compensating Antenna Crosstalk And Mismatch Effects In Advanced Antenna System
(
- Master (Two yrs)
-
Mark
Implementation and Benchmarking of a Crypto Processor for a NB-IoT SoC Platform
(
- Master (Two yrs)
-
Mark
RF system for mmWave massive MIMO
(
- Master (Two yrs)
-
Mark
Direct measurement of fluorescence lifetime using high speed data acquisition
(
- Master (Two yrs)
-
Mark
Hardware-software model co-simulation for GPU IP development
(
- Master (Two yrs)
- 2017
-
Mark
Frequency Tracking Using Digital Cavities
(
- Bach. Degree
-
Mark
FPGA-BASED HYBRID COMPUTING FOR ESS LINAC SIMULATOR.
(
- Master (Two yrs)
-
Mark
Virtual Cycle-accurate Hardware and Software Co-simulation Platform for Cellular IoT
(
- Master (Two yrs)
-
Mark
Evaluation of flexible SPA based LPDC decoder using hardware friendly approximation methods
(
- Master (Two yrs)
- 2016
-
Mark
Design and Implementation of a 2-Channel High Precision and High Speed Digitizing system
(
- Master (Two yrs)
-
Mark
Memory Energy Optimizations for IoT Processors
(
- Master (Two yrs)
- 2015
-
Mark
Real-Time Lossless Compression of SoC Trace Data
(
- Master (Two yrs)