Using Approximate Computing Circuits to Optimize Power of an ASIC
(2023) EITM02 20222Department of Electrical and Information Technology
- Abstract
- The growing demand for network cameras to support real-time image processing
and machine-learning applications has created a need for low-power solutions.
Although technology scaling makes complex computations feasible, voltage scaling
is limited, leading to higher power density and dark silicon problems. One potential
solution is the use of Approximate Arithmetic Circuits (AACs). This effectively
reduces the number of logic gates required to perform arithmetic computations on
ASICs. This technique is particularly suitable for image applications because the
human eye’s perceptual tolerance makes a degree of error admissible.
In this thesis, the Lanczos scaling is selected as the image application to evalu-
ate the feasibility of... (More) - The growing demand for network cameras to support real-time image processing
and machine-learning applications has created a need for low-power solutions.
Although technology scaling makes complex computations feasible, voltage scaling
is limited, leading to higher power density and dark silicon problems. One potential
solution is the use of Approximate Arithmetic Circuits (AACs). This effectively
reduces the number of logic gates required to perform arithmetic computations on
ASICs. This technique is particularly suitable for image applications because the
human eye’s perceptual tolerance makes a degree of error admissible.
In this thesis, the Lanczos scaling is selected as the image application to evalu-
ate the feasibility of applying AACs to trade off accuracy for power. To quantita-
tively evaluate the impact on image quality introduced by AAC errors, arithmetic
accuracy metrics and image quality metrics are studied to find a correlation be-
tween them. Furthermore, power simulations are conducted on AACs using sub-10
nm technology to validate the power savings the chosen fabrication node achieves.
Finally, the exact multipliers in the Lanczos scaling hardware are replaced with a
selection of AACs, and then the system-level power consumption is assessed when
scaling actual images.
The outcome of this study shows that the image scaling application produces a
power saving exceeding 50% while maintaining a high Structural Similarity Index
Metric (SSIM) of up to 0.9. This finding contributes to understanding the potential
of an AAC in reducing power consumption in image processing circuits, paving
the way for future advancements in approximate computing techniques. (Less) - Popular Abstract
- In today’s technology-driven world, images surround us in various forms, from
social media posts to security camera feeds. Behind the scenes, powerful compu-
tational processes work tirelessly to enhance and analyze these images in real time.
However, this quest for image perfection comes at a cost - power consumption. As
our appetite for image processing grows, so does the need for power-efficient solu-
tions to curb the skyrocketing power demands.
In the pursuit of power efficiency, engineers are faced with a conundrum. While
technology advancements enable complex computations, scaling down voltage or
frequency to reduce power is increasingly challenging. This has led to the emer-
gence of Approximate Arithmetic Circuits... (More) - In today’s technology-driven world, images surround us in various forms, from
social media posts to security camera feeds. Behind the scenes, powerful compu-
tational processes work tirelessly to enhance and analyze these images in real time.
However, this quest for image perfection comes at a cost - power consumption. As
our appetite for image processing grows, so does the need for power-efficient solu-
tions to curb the skyrocketing power demands.
In the pursuit of power efficiency, engineers are faced with a conundrum. While
technology advancements enable complex computations, scaling down voltage or
frequency to reduce power is increasingly challenging. This has led to the emer-
gence of Approximate Arithmetic Circuits (AACs), prioritizing power efficiency
over absolute accuracy. By introducing controlled errors into arithmetic computa-
tions, AACs significantly reduce the logic gates needed for image processing while
maintaining perceptible image quality. This breakthrough opens new possibilities
for power-conscious image applications.
In this thesis, meticulous studies are conducted to assess the impact of approx-
imation on image quality and power consumption by integrating AACs in image
resizing techniques, such as the widely used Lanczos scaling. By exploring the cor-
relation between arithmetic accuracy metrics and image quality metrics, optimal
power savings can be achieved while preserving visual fidelity.
AACs offer a promising solution to address the power challenges in image
processing. By leveraging the innate error tolerance of human perception, approx-
imate circuits pave the way for greener and more sustainable image-processing
technologies. With AACs, we can build power-efficient systems that meet the
ever-growing demands of image applications while reducing power consumption.
This research sets the stage for future advancements in approximate computing
techniques, shaping a world where power efficiency and innovation go hand in
hand. (Less)
Please use this url to cite or link to this publication:
http://lup.lub.lu.se/student-papers/record/9134553
- author
- Nuggehalli Srinivasa, Padmashree LU and Hsing, Shi-Tien LU
- supervisor
-
- Liang Liu LU
- organization
- course
- EITM02 20222
- year
- 2023
- type
- H2 - Master's Degree (Two Years)
- subject
- keywords
- ASIC, Power, Optimization, Approximate Arithmetic Circuits, Approximate Computing, Technology
- report number
- LU/LTH-EIT 2023-938
- language
- English
- id
- 9134553
- date added to LUP
- 2023-08-29 11:10:53
- date last changed
- 2023-08-29 11:10:53
@misc{9134553,
abstract = {{The growing demand for network cameras to support real-time image processing
and machine-learning applications has created a need for low-power solutions.
Although technology scaling makes complex computations feasible, voltage scaling
is limited, leading to higher power density and dark silicon problems. One potential
solution is the use of Approximate Arithmetic Circuits (AACs). This effectively
reduces the number of logic gates required to perform arithmetic computations on
ASICs. This technique is particularly suitable for image applications because the
human eye’s perceptual tolerance makes a degree of error admissible.
In this thesis, the Lanczos scaling is selected as the image application to evalu-
ate the feasibility of applying AACs to trade off accuracy for power. To quantita-
tively evaluate the impact on image quality introduced by AAC errors, arithmetic
accuracy metrics and image quality metrics are studied to find a correlation be-
tween them. Furthermore, power simulations are conducted on AACs using sub-10
nm technology to validate the power savings the chosen fabrication node achieves.
Finally, the exact multipliers in the Lanczos scaling hardware are replaced with a
selection of AACs, and then the system-level power consumption is assessed when
scaling actual images.
The outcome of this study shows that the image scaling application produces a
power saving exceeding 50% while maintaining a high Structural Similarity Index
Metric (SSIM) of up to 0.9. This finding contributes to understanding the potential
of an AAC in reducing power consumption in image processing circuits, paving
the way for future advancements in approximate computing techniques.}},
author = {{Nuggehalli Srinivasa, Padmashree and Hsing, Shi-Tien}},
language = {{eng}},
note = {{Student Paper}},
title = {{Using Approximate Computing Circuits to Optimize Power of an ASIC}},
year = {{2023}},
}