High Level Synthesis for ASIC and FPGA

Abstract

This thesis aims to evaluate the performance of Siemens’ High Level Synthesis
(HLS) tool Catapult. HLS can be considered the next step up in abstraction
level from writing traditional Register Transfer Level (RTL) code which is time
consuming and error prone. The promise of HLS is to speed up the process of
designing integrated circuits by lifting the abstraction level so the design can be
coded fully in a high-level programming language such as C++. RTL code can be
generated from the high-level description and then synthesized. The goal of this
thesis is to evaluate if HLS can be used to efficiently share code for different target
platforms. The compared platforms are Application Specific Integrated Circuit
(ASIC) and Field Programmable Gate Array (FPGA). Being able to use the same
code base for both could enable prototyping on FPGA and faster development
cycles. To evaluate the suitability of sharing code this way, a case study of a
symmetric Finite Impulse Response (FIR) filter was conducted. This is a suitable
design to compare because it has clear best implementations that differ between
ASIC and FPGA. For FPGA it should be implemented using DSP-slices. Since an
ASIC is fully custom it should be implemented with multipliers and adders. To
achieve this, the same C++ source code was used with different pragmas depending
on platform and the generated RTL was either implemented on FPGA or estimated
area for ASIC. No backend implementation was done for ASIC. The result showed a
need for slightly different code in the two cases to get the intended implementation.
DSP-slices were not generated for FPGA below certain bit-widths. The results
varied greatly depending on the language chosen for the generated RTL-code,
VHDL or Verilog. In conclusion the C++ source code could only be optimized for
one of the targets at a time. Using the same source for FPGA and ASIC would
result in worse results for one of them.

Popular Abstract

Advancements in technology in the past 100 years have been huge and affected our
way of living a lot. More and more things are becoming "smart", it’s not only our
phones, but also things like lighting, cars, household appliances and much more.
An important building block behind these inventions is the integrated circuit (IC).
The innovation that lets multiple transistors be integrated on the same piece of
silicon. This makes the chip smaller, faster, and more energy efficient. As a result
the integrated circuits could also do more for the same cost. The development has
continued rapidly with new smaller and even faster techniques to enable better
products to manufacturers and then customers. But this fast development has
also made the design of the circuits so much more complex. Chips can consist
of billions of transistor, which is a staggering number. To be able to handle this
increasing complexity computer aided tools are needed. It is simple impossible to
do without them. The development of these tools is in some way limiting what
can be achieved in the designing of an integrated circuit, and therefore essential
to the further improvements. This thesis examines one of these tools, Siemens’
Catapult High Level Synthesis tool. The purpose of this tool is to speed up the
development of IC’s by letting the designers specify in a higher level programming
language than what has been done traditionally. Another use of this could be to
unify code targeted at different platforms to reduce effort and code maintenance.
Two fundamentally different target platforms that are compared in this thesis is
FPGA and ASIC. These two are quite different from each other, but one of the
key differences is that an ASIC can never be changed after production. It will
contain exactly the functionality that was designed. An FPGA on the other hand,
is designed to be highly configurable and can be reprogrammed freely to implement
new functionality. ASICs are also faster and more efficient than FPGA, but on
the backside also much more expensive and take longer to develop. Being able to
use the same code for both of these platforms would mean that a design could be
prototyped on FPGA before producing an ASIC, thus reducing the risk of bugs in
the more expensive chip. This thesis uses a case study of a common digital signal
processing block, a symmetric finite impulse response filter, to explore whether
the same code can be efficiently used for both platforms.

• author: Heyden, Malin
• supervisor: Liang Liu
• organization: Department of Electrical and Information Technology
• course: EITM01 20211
• year: 2023
• type: H2 - Master's Degree (Two Years)
• subject: Technology and Engineering
• keywords: HLS, high level synthesis, asic, fpga, catapult, filter, sfir
• report number: LU/LTH-EIT 2023-925
• language: English
• id: 9126669
• date added to LUP: 2023-06-20 15:40:13
• date last changed: 2023-06-20 15:40:13