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Case study on Universal Verification Methodology(UVM) SystemC testbench for RTL verification

Chacko, Kevin Skaria LU (2019) EITM02 20191
Department of Electrical and Information Technology
Abstract
This Master’s thesis aims to conduct a case study on using Universal Verification Methodology (UVM) in SystemC for Register-Transfer Level (RTL) verification. Verification of ASICs is very important nowadays especially in terms of production costs, time to market and the sustainability of products. As Moore’s Law is in motion, verification gets large, complex, and time-consuming. Re-usability and simulation performance of testbenches are key areas for improvement. Accellera Systems Initiative, a standard organization that supports user and vendor standards in the field of EDA and ICs has released UVM in SystemC as a Beta version. Since SystemVerilog UVM testbenches have been around in industries for several years in different performance... (More)
This Master’s thesis aims to conduct a case study on using Universal Verification Methodology (UVM) in SystemC for Register-Transfer Level (RTL) verification. Verification of ASICs is very important nowadays especially in terms of production costs, time to market and the sustainability of products. As Moore’s Law is in motion, verification gets large, complex, and time-consuming. Re-usability and simulation performance of testbenches are key areas for improvement. Accellera Systems Initiative, a standard organization that supports user and vendor standards in the field of EDA and ICs has released UVM in SystemC as a Beta version. Since SystemVerilog UVM testbenches have been around in industries for several years in different performance optimized versions, one of these versions is implemented in UVM SystemC to study if the same optimizations are possible. This will also enable to have a common language platform for SystemC Register-Transfer Level (RTL) and RTL testbench development. In order to simulate two different hardware modeling languages in an EDA simulator, 3 different methods of interfacing UVM SystemC with SystemVerilog RTL have been explored: UVM-Multi Language (ML), Beta over Legacy (BoL), and Standard Co-Emulation Interface(SCE-MI). Based on simplicity and simulation time the oL interface has been characterized for a better option. Moreover, knowing the relationship of SystemC simulation time with timing accuracy, a performance comparison with SystemVerilog UVM has helped to understand the bottleneck of SystemC testbench with cycle-accurate interfaces as compared to SystemVerilog interfaces where the simulator tool perform optimizations in context switching. From the results of the performance comparison, this study proposes a direction in using a hybrid testbench model where the stimulus and response data parts of the testbench are still in SystemC TLM whereas the cycle accurate interfaces with the RTL are in SystemVerilog. (Less)
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As the digital electronics and semiconductor industries tries to follow the Moores Law: "The number of transistors and resistors on a chip doubles every 24 months", the verification process of these chips gets large and more complex. The need for verification engineers in an ASIC/IC development project has surpassed the design engineers since a few years for the same reason. Nowadays electronic industries compete with each other to reach the market first and give the most innovative and efficient products. It can be seen with the new standards released every decade in mobile communications: GSM, 3G, 4G and now 5G. To make sure these industries meet the consumers demands for high speed... (More)
You need to give up something to achieve something.

As the digital electronics and semiconductor industries tries to follow the Moores Law: "The number of transistors and resistors on a chip doubles every 24 months", the verification process of these chips gets large and more complex. The need for verification engineers in an ASIC/IC development project has surpassed the design engineers since a few years for the same reason. Nowadays electronic industries compete with each other to reach the market first and give the most innovative and efficient products. It can be seen with the new standards released every decade in mobile communications: GSM, 3G, 4G and now 5G. To make sure these industries meet the consumers demands for high speed communication, they need to find faster and efficient ways of designing and verifying their products. This would be the context of this thesis work: to find a direction on how to reduce the verification time of large and complex digital hardware designs. Digital Circuits are designed with Hardware Description Language (HDL) which is like a programming language to implement a Register-Transfer Level(RTL) abstraction model of data flow and timing of a circuit. These HDL’s can be simulated to check their correctness with testbenches. The traditional testbenches are usually written with HDL languages in different standards or methodologies to interface better with the Design Under Test (DUT). Therefore if an HDL testbench can be adapted to a more abstract language such as SystemC based on C++, it will be able to compile and sequentially run them much faster and efficiently. HDL Testbench languages typically vary based on their size and complexity in verifying hardware designs, smaller designs use VHDL/Verilog with no specific standard or methodology whereas bigger designs uses SystemVerilog in Universal Verification Methodology (UVM) framework. These languages are tools of a trade like carpentry and the methodologies explains how efficiently the trade can build something big like a house. This thesis work will verify a RTL hardware design of Ericsson with a testbench on SystemC Universal Verification Methodology(UVM) framework and compare its simulation time to already existing SystemVerilog UVM framework. The study of comparing simulation performances will help to understand the bottleneck of using UVM SystemC and provide a direction on how to improve the current best performance. (Less)
Please use this url to cite or link to this publication:
author
Chacko, Kevin Skaria LU
supervisor
organization
course
EITM02 20191
year
type
H2 - Master's Degree (Two Years)
subject
report number
LU/LTH-EIT 2019-696
language
English
id
8980633
date added to LUP
2019-09-05 16:43:28
date last changed
2019-09-05 16:43:28
@misc{8980633,
  abstract     = {This Master’s thesis aims to conduct a case study on using Universal Verification Methodology (UVM) in SystemC for Register-Transfer Level (RTL) verification. Verification of ASICs is very important nowadays especially in terms of production costs, time to market and the sustainability of products. As Moore’s Law is in motion, verification gets large, complex, and time-consuming. Re-usability and simulation performance of testbenches are key areas for improvement. Accellera Systems Initiative, a standard organization that supports user and vendor standards in the field of EDA and ICs has released UVM in SystemC as a Beta version. Since SystemVerilog UVM testbenches have been around in industries for several years in different performance optimized versions, one of these versions is implemented in UVM SystemC to study if the same optimizations are possible. This will also enable to have a common language platform for SystemC Register-Transfer Level (RTL) and RTL testbench development. In order to simulate two different hardware modeling languages in an EDA simulator, 3 different methods of interfacing UVM SystemC with SystemVerilog RTL have been explored: UVM-Multi Language (ML), Beta over Legacy (BoL), and Standard Co-Emulation Interface(SCE-MI). Based on simplicity and simulation time the oL interface has been characterized for a better option. Moreover, knowing the relationship of SystemC simulation time with timing accuracy, a performance comparison with SystemVerilog UVM has helped to understand the bottleneck of SystemC testbench with cycle-accurate interfaces as compared to SystemVerilog interfaces where the simulator tool perform optimizations in context switching. From the results of the performance comparison, this study proposes a direction in using a hybrid testbench model where the stimulus and response data parts of the testbench are still in SystemC TLM whereas the cycle accurate interfaces with the RTL are in SystemVerilog.},
  author       = {Chacko, Kevin Skaria},
  language     = {eng},
  note         = {Student Paper},
  title        = {Case study on Universal Verification Methodology(UVM) SystemC testbench for RTL verification},
  year         = {2019},
}